# # fadc250 config file - EXAMPLE # # this file contains settings for # fADC250 - JLAB VXS Flash ADC 12-bit 250 Msps 16 ch # # format: # ~~~~~~~ # CRATE rocbcal1 <- ROC name, crate name, usually IP name # FADC250_ALLSLOTS <- just keyword - all settings after this line will be implemented # for all slots, till FADC250_SLOTS will be met # FADC250_SLOTS 3 8 15 <- slot_numbers - in which next settings will be implemented # till file ends or next FADC250_SLOTS will be met # # FADC250_F_REV 0x0216 <- firmware revision (0x0 Bits:7-0) # FADC250_B_REV 0x0908 <- board revision (0x0 Bits:15-8) # FADC250_ID 0xfadc <- board type (0x0 Bits:31-16) # # FADC250_MODE 1 <- process mode: 1-4 (0x10C Bits:2-0) # FADC250_W_OFFSET 50 <- number of sample back from trigger point. (0x120) # (in Manual it is PL=Trigger_Window(ns) * 250MHz) # FADC250_W_WIDTH 49 <- number of ADC sample to include in trigger window. (0x11C) # (in M: PTW=Trigger_Window(ns) * 250MHz, minimum is 6) # FADC250_NSB 3 <- number of sample before trigger point to include in data processing. (0x124) # This include the trigger Point. (minimum is 2 in all mode) # FADC250_NSA 6 <- number of sample after trigger point to include in data processing. (0x128) # Minimum is (6 in mode 2) and ( 3 in mode 0 and 1). # Number of sample report is 1 more for odd and 2 more for even NSA number. # FADC250_NPEAK 1 <- number of Pulses in Mode 2 and 3. (0x10C Bits:6-5) # # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - channels ## # FADC250_ADC_MASK 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 <- channel enable mask (0x110) # FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- trigger enable mask # (channel includes in global trigger, if bit set to 1) # FADC250_TET 110 <- board Trigger Energy Threshold (TET), same for all 16 channels # FADC250_CH_TET 0 110 <- channel# and TET_value for this channel # FADC250_ALLCH_TET 111 222 2 3 4 5 6 7 8 9 10 11 12 13 14 15 <- 16 TETs (0x12C - 0x148) # # FADC250_DAC 3300 <- board DAC, one and the same for all 16 channels # FADC250_CH_DAC 0 3300 <- channel# and DAC_value for this channel # FADC250_ALLCH_DAC 3300 3280 3310 3280 3310 3280 3310 3280 3300 3280 3300 3280 3310 3280 3310 3280 <- 16 DACs # # FADC250_PED 210 <- board Pedestals, same for all channels # FADC250_CH_PED 0 210 <- channel# and Pedestal_value for this channel # FADC250_ALLCH_PED 210 220 210 215 215 220 220 210 210 215 215 220 220 210 215 220 <- 16 PEDs CRATE rocfcal11 ############################ FADC250_SLOTS 3 ######################### FADC250_ALLCH_DAC 3336 3355 3376 3358 3369 3392 3361 3388 3358 3385 3351 3351 3349 3361 3374 3380 ############################ FADC250_SLOTS 4 ######################### FADC250_ALLCH_DAC 3335 3339 3384 3356 3368 3356 3378 3369 3373 3382 3382 3374 3352 3355 3381 3348 ############################ FADC250_SLOTS 5 ######################### FADC250_ALLCH_DAC 3379 3388 3386 3407 3385 3365 3392 3374 3387 3386 3402 3380 3376 3385 3397 3398 ############################ FADC250_SLOTS 6 ######################### FADC250_ALLCH_DAC 3387 3394 3382 3379 3386 3374 3353 3353 3359 3381 3358 3377 3363 3353 3363 3388 ############################ FADC250_SLOTS 7 ######################### FADC250_ALLCH_DAC 3376 3381 3362 3373 3379 3383 3396 3367 3380 3332 3339 3378 3357 3374 3384 3375 ############################ FADC250_SLOTS 8 ######################### FADC250_ALLCH_DAC 3395 3384 3359 3393 3365 3368 3379 3375 3385 3418 3375 3387 3395 3393 3349 3399 ############################ FADC250_SLOTS 9 ######################### FADC250_ALLCH_DAC 3369 3359 3399 3397 3385 3382 3363 3373 3341 3407 3375 3366 3377 3365 3356 3366 ############################ FADC250_SLOTS 10 ######################### FADC250_ALLCH_DAC 3367 3379 3347 3346 3383 3377 3370 3380 3384 3365 3376 3370 3350 3395 3359 3381 ############################ FADC250_SLOTS 13 ######################### FADC250_ALLCH_DAC 3361 3367 3354 3348 3368 3353 3355 3359 3368 3368 3370 3367 3366 3361 3355 3381 ############################ FADC250_SLOTS 14 ######################### FADC250_ALLCH_DAC 3375 3363 3369 3369 3394 3340 3379 3375 3366 3379 3367 3342 3356 3370 3360 3361 ############################ FADC250_SLOTS 15 ######################### FADC250_ALLCH_DAC 3373 3382 3367 3373 3380 3386 3381 3365 3378 3375 3378 3377 3384 3376 3370 3362 ############################ FADC250_SLOTS 16 ######################### FADC250_ALLCH_DAC 3363 3370 3376 3348 3389 3353 3377 3374 3370 3372 3368 3364 3382 3397 3375 3364 ############################ FADC250_SLOTS 17 ######################### FADC250_ALLCH_DAC 3342 3371 3358 3352 3365 3387 3327 3353 3356 3355 3361 3353 3386 3359 3351 3375 ############################ FADC250_SLOTS 18 ######################### FADC250_ALLCH_DAC 3319 3370 3350 3366 3366 3359 3379 3367 3365 3348 3366 3371 3370 3354 3392 3363 ############################ FADC250_SLOTS 19 ######################### FADC250_ALLCH_DAC 3370 3365 3378 3378 3342 3379 3364 3353 3385 3389 3348 3360 3364 3358 3365 3371