#! Run type:: PHYSICS_8 Config:: TRG_FCAL_BCAL_m8_b1bf1.conf #! CONFIG FILE:: /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/TRG_FCAL_BCAL_m8_b1bf1.conf #! (Re)Created:: on Wed Apr 29 12:06:51 EDT 2015 #! # DSC2_WIDTH 20 40 <- TDC width (ns), TRG width (ns) # DSC2_THRESHOLD 20 50 <- board threshold: TDC threshold (mV), TRG threshold (mV) # # TS_TRIG_TYPE 1 - Internal Pulser # 2 - External FP # 4 - GTP # 6 - GTP + External # # # TS_FP_INPUTS - List of enabled FP inputs # # # TS_SOFT_TRIG # Trigger type (type 1 or 2 for playback) # Number of events to trigger # Period multiplier (depends on range 0-0x7FFF) # Range 1 - min 120ns, increments of 30ns up to 983.13u # 2 - min 120ns, increments of 30.72us up to 1.007s # # # TI_MASTER 1 - Stand alone with master TI # # TI_MASTER_TRIG 1 - soft, 2 - external pulser, 3 - playback # # TI_SOFT_TRIG # Trigger type (type 1 or 2 for playback) # Number of events to trigger # Period multiplier (depends on range 0-0x7FFF) # Range 1 - min 120ns, increments of 30ns up to 983.13u # 2 - min 120ns, increments of 30.72us up to 1.007s # # F1TDC_CLOCK 0 <- Clock Source (0 = Internal 32 MHz) # (1 = External 31.25 MHz) # F1TDC_VERSION 2 <- Module Version (2 = High Resolution, synchronous, 32 channels) # (3 = Normal Resolution, synchronous, 48 channels) # set bin size from 0.056 to 0.058 -> Beni! # F1TDC_BIN_SIZE 0.058 <- Bin size (ns) # F1TDC_LATENCY 3000.0 <- Trigger latency (ns) # F1TDC_WINDOW 1000.0 <- Trigger window (ns) ========================== TRIGGER ========================== #CALIBRATION 1 TS_TRIG_TYPE 2 TS_FP_INPUTS 9 10 #TS_FP_DELAY 9 24 #TS_FP_DELAY 10 50 #TS_FP_DELAY 9 27 #TS_FP_DELAY 10 53 #04/15/2016 TS_FP_DELAY 9 23 TS_FP_DELAY 10 44 TS_FP_DELAY 3 427 TS_SOFT_TRIG 1 0 0x1F 1 TS_TD_SLOTS 7 8 14 # SSP SLOT FIBER_EN SUM_ENABLE SSP_SLOT 8 0xFF 1 # TYPE DELAY INT_WIDTH ENABLE TRIG_EQ PS 35 10 0 TRIG_EQ BCAL_E 15 20 1 TRIG_EQ BCAL_C 20 0 0 TRIG_EQ FCAL 8 10 0 TRIG_EQ ST 30 10 0 TRIG_EQ TOF 20 10 0 # TRIG_EQ BCAL_E 20 20 1 # TRIG_EQ FCAL 8 10 1 # TYPE LATENCY WIDTH FCAL_E BCAL_E EN_THR NHIT LANE FCAL_EMIN FCAL_EMAX BCAL_EMIN BCAL_EMAX PATTERN TRIG_TYPE BFCAL 440 5 20 0 36000 -1 -5 200 65535 0 65535 #TS_GTP_PRES 6 1 #TS_GTP_PRES 0 2 #TS_GTP_PRES 1 2 #TS_GTP_PRES 2 2 #TS_GTP_PRES 3 2 #TS_GTP_PRES 0 10 #TS_GTP_PRES 1 5 #TS_GTP_PRES 2 5 TRIG_DELAY 0 DAC_CALIB 0 TI_FIBER_LATENCY_OFFSET 0x98 TS_COIN_WIND 15 # TEST 2, THR = 3 TS_TRIG_HOLD 1 10 0 TS_TRIG_HOLD 2 127 0 TS_TRIG_HOLD 4 40 0 TS_TRIG_HOLD 3 2 1 # TS_SYNC_INT 1000 # 2/7/16 changed to 5000 TS_SYNC_INT 5000 TI_MASTER 0 TI_MASTER_TRIG 1 TI_FP_INPUTS 3 # TI_SOFT_TRIG 1 10000 0x7FFF 1 TI_SOFT_TRIG 1 10000 0x600 1 BLOCKLEVEL 1 BUFFERLEVEL 1 ========================== GLOBAL ========================== F1TDC_BIN_SIZE 0.058 ========================== BCAL ========================== # change offset from 905 to 885 -> Beni 6.10.2014 afternoon # also change NSB and NSA from 3/6 to 5/40 FADC250_MODE 10 # Changed from 825 to 820 (2/26/15) # FADC250_W_OFFSET 820 # Changed from 820 to 815 (12/15/16) FADC250_W_OFFSET 815 # MMD 2017-01-27 FADC250_W_WIDTH 100 FADC250_NSB 1 FADC250_NSA 26 FADC250_NPEAK 1 FADC250_NSAT 2 # MMD threshold from 110 to 105 (2014-12-05) # Jon Z: reduce to 30 for pedestal width studies # (in other words: should be reading out every channel) FADC250_READ_THR 10 FADC250_TRIG_BL 100 FADC250_TRIG_THR 120 FADC250_TRIG_NSB 3 FADC250_TRIG_NSA 19 FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default FADC250_COM_VER default FADC250_USER_DIR /gluex/CALIB/ALL/user FADC250_USER_VER # F1 TDC #change latency from 900. to 3540. and window from 500 to 1000 ->Beni # F1TDC_WINDOW 1000. # Changed from 1000 to 400 (12/17/2016) F1TDC_WINDOW 400. F1TDC_LATENCY 3400. # set bin size from 0.056 to 0.058 -> Beni! F1TDC_CLOCK 1 # LE discriminator DSC2_WIDTH 20 40 DSC2_THRESHOLD 35 50 DSC2_COM_DIR /gluex/CALIB/ALL/dsc/default DSC2_COM_VER default