c#! Run type:: PHYSICS_8 Config:: TRG_FCAL_BCAL_m8_b1bf1.conf #! CONFIG FILE:: /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/TRG_FCAL_BCAL_m8_b1bf1.conf #! (Re)Created:: on Wed Apr 29 12:06:51 EDT 2015 #! # DSC2_WIDTH 20 40 <- TDC width (ns), TRG width (ns) # DSC2_THRESHOLD 20 50 <- board threshold: TDC threshold (mV), TRG threshold (mV) # # TS_TRIG_TYPE 1 - Internal Pulser # 2 - External FP # 4 - GTP # 6 - GTP + External # # # TS_FP_INPUTS - List of enabled FP inputs # # # TS_SOFT_TRIG # Trigger type (type 1 or 2 for playback) # Number of events to trigger # Period multiplier (depends on range 0-0x7FFF) # Range 1 - min 120ns, increments of 30ns up to 983.13u # 2 - min 120ns, increments of 30.72us up to 1.007s # # # TI_MASTER 1 - Stand alone with master TI # # TI_MASTER_TRIG 1 - soft, 2 - external pulser, 3 - playback # # TI_SOFT_TRIG # Trigger type (type 1 or 2 for playback) # Number of events to trigger # Period multiplier (depends on range 0-0x7FFF) # Range 1 - min 120ns, increments of 30ns up to 983.13u # 2 - min 120ns, increments of 30.72us up to 1.007s # # F1TDC_CLOCK 0 <- Clock Source (0 = Internal 32 MHz) # (1 = External 31.25 MHz) # F1TDC_VERSION 2 <- Module Version (2 = High Resolution, synchronous, 32 channels) # (3 = Normal Resolution, synchronous, 48 channels) # set bin size from 0.056 to 0.058 -> Beni! # F1TDC_BIN_SIZE 0.058 <- Bin size (ns) # F1TDC_LATENCY 3000.0 <- Trigger latency (ns) # F1TDC_WINDOW 1000.0 <- Trigger window (ns) ========================== TRIGGER ========================== #CALIBRATION 1 TS_TRIG_TYPE 2 TS_FP_INPUTS 5 6 # TS_FP_INPUTS 3 9 10 12 #Cosmic test 11/11/2016 TS_FP_DELAY 6 370 TS_FP_DELAY 3 427 TS_SOFT_TRIG 1 0 0x1F 1 # TS_TD_SLOTS 8 14 7 TS_TD_SLOTS 4 14 9 # TS_TD_SLOTS 3 4 7 8 14 # TS_TD_SLOTS 3 4 7 8 9 10 14 # TS_TD_SLOTS 9 3 10 8 6 4 5 7 14 # ALL CRATES # TS_TD_SLOTS 8 14 7 # TS_TD_SLOTS 9 3 10 8 6 5 7 14 # SSP SLOT FIBER_EN SUM_ENABLE SSP_SLOT 7 0x1 0 # TYPE DELAY INT_WIDTH ENABLE TRIG_EQ PS 20 5 0 TRIG_EQ BCAL_E 20 20 0 TRIG_EQ BCAL_C 12 0 0 TRIG_EQ FCAL 0 10 0 TRIG_EQ ST 22 3 0 TRIG_EQ TOF 12 10 1 TRIG_EQ TAGH 96 0 0 # TYPE LATENCY WIDTH FCAL_E BCAL_E EN_THR NHIT LANE FCAL_EMIN FCAL_EMAX BCAL_EMIN BCAL_EMAX PATTERN TRIG_TYPE TOF 450 20 1300 1900 1100 3 0 # TS_GTP_PRES 6 1 # TS_GTP_PRES 0 6 #TS_GTP_PRES 0 2 #TS_GTP_PRES 1 2 #TS_GTP_PRES 2 2 #TS_GTP_PRES 3 2 #TS_GTP_PRES 0 10 #TS_GTP_PRES 1 5 #TS_GTP_PRES 2 5 TRIG_DELAY 0 DAC_CALIB 0 TI_FIBER_LATENCY_OFFSET 0x98 TS_COIN_WIND 15 # TS_TRIG_HOLD 63 0 # TS_TRIG_HOLD 62 1 TS_TRIG_HOLD 1 5 1 # TS_SYNC_INT 5000 BLOCKLEVEL 40 BUFFERLEVEL 4 ========================== GLOBAL ========================== F1TDC_BIN_SIZE 0.058 ========================== TOF ========================== # change latency and width from 510/200 to 910/100 # and change NSB and NSA from 3/6 to 5/20 # btw. it is BENI # changed NSB & NSA from 5/20 to 10/45 (eugenio) FADC250_MODE 9 # FADC250_W_OFFSET 810 # Changed from 820 to 815 (12/15/16) FADC250_W_OFFSET 800 # FADC250_W_WIDTH 100 # Changed from 100 to 70 (12/17/2016) # Changed from 70 to 80 (02/01/2017) FADC250_W_WIDTH 120 FADC250_NSB 1 FADC250_NSA 10 FADC250_NPEAK 3 FADC250_NSAT 2 FADC250_READ_THR 160 FADC250_TRIG_BL 100 FADC250_TRIG_THR 360 FADC250_TRIG_NSB 3 FADC250_TRIG_NSA 15 FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default FADC250_COM_VER default FADC250_USER_DIR /home/ FADC250_USER_VER # CTP_BCAL_THR 56000 # LE discriminator DSC2_WIDTH 20 40 # Default DSC2_THRESHOLD -12 -12 DSC2_COM_DIR /gluex/CALIB/ALL/dsc/default DSC2_COM_VER default # CAEN 1290 #TDC1290_W_WIDTH 750 #TDC1290_W_WIDTH 3800 # Changed TDC1290_W_WIDTH from 3800 to 1000 (12/17/2016) # Changed TDC1290_W_WIDTH from 1000 to 800 (02/01/2017) # Changed TDC1290_W_WIDTH from 800 to 400 (01/27/2020) TDC1290_W_WIDTH 400 #TDC1290_W_OFFSET -1750 #TDC1290_W_OFFSET -3640 # change TDC1290_W_OFFSET from -3660 to -3410 (01/27/2020) TDC1290_W_OFFSET -3410 TDC1290_W_EXTRA 25 TDC1290_W_REJECT 50 TDC1290_BLT_EVENTS 1 TDC1290_N_HITS 64 TDC1290_ALMOSTFULL 16384 TDC1290_OUT_PROG 2 TDC1290_A24_A32 2 TDC1290_SNGL_BLT 3 TDC1290_SST_RATE 0 TDC1290_BERR_FIFO 1 TDC1290_EDGE 2 TDC1290_INL 1 TDC1290_RC 3 0 5 1 4 3 TDC1290_RC 3 1 5 5 1 3 TDC1290_RC 3 2 7 2 7 4 TDC1290_RC 3 3 2 2 7 7 TDC1290_RC 4 0 0 1 6 3 TDC1290_RC 4 1 0 6 1 4 TDC1290_RC 4 2 3 2 0 3 TDC1290_RC 4 3 1 1 5 7 TDC1290_RC 5 0 6 0 1 6 TDC1290_RC 5 1 5 4 1 6 TDC1290_RC 5 2 2 1 2 3 TDC1290_RC 5 3 3 1 7 5 TDC1290_RC 6 0 1 4 6 6 TDC1290_RC 6 1 2 5 0 6 TDC1290_RC 6 2 7 0 7 5 TDC1290_RC 6 3 5 7 1 3 TDC1290_RC 7 0 3 1 6 6 TDC1290_RC 7 1 3 0 3 3 TDC1290_RC 7 2 7 4 1 3 TDC1290_RC 7 3 0 2 7 7 TDC1290_RC 8 0 7 7 0 4 TDC1290_RC 8 1 5 1 7 7 TDC1290_RC 8 2 3 0 4 2 TDC1290_RC 8 3 0 0 0 4 ========================== MUON ========================== # CDC_short 3 # CDC_long 6 # FDC_short 4 # FDC_amp_short 5 # FDC_sum_long 7 # FDC_amp_long 8 FADC125_MODE 3 FADC125_W_OFFSET 438 FADC125_W_WIDTH 200 FADC125_IE 200 FADC125_NPEAK 1 FADC125_PG 4 FADC125_P1 4 FADC125_P2 4 FADC125_IBIT 4 FADC125_ABIT 3 FADC125_PBIT 0 FADC125_TH 60 FADC125_TL 15 FADC125_THR 500 FADC125_DAC 800 FADC125_COM_DIR /gluex/CALIB/ALL/fadc125/default FADC125_COM_VER default FADC125_USER_DIR /gluex/ FADC125_USER_VER DSC2_WIDTH 20 40 DSC2_THRESHOLD 35 50 DSC2_COM_DIR /gluex/CALIB/ALL/dsc/default DSC2_COM_VER