# DSC2_WIDTH 20 40 <- TDC width (ns), TRG width (ns) # DSC2_THRESHOLD 20 50 <- board threshold: TDC threshold (mV), TRG threshold (mV) # # TS_TRIG_TYPE 1 - Internal Pulser # 2 - External FP # 4 - GTP # 6 - GTP + External # # # TS_FP_INPUTS - List of enabled FP inputs # # # TS_SOFT_TRIG # Trigger type (type 1 or 2 for playback) # Number of events to trigger # Period multiplier (depends on range 0-0x7FFF) # Range 1 - min 120ns, increments of 30ns up to 983.13u # 2 - min 120ns, increments of 30.72us up to 1.007s # # # TI_MASTER 1 - Stand alone with master TI # # TI_MASTER_TRIG 1 - soft, 2 - external pulser, 3 - playback # # TI_SOFT_TRIG # Trigger type (type 1 or 2 for playback) # Number of events to trigger # Period multiplier (depends on range 0-0x7FFF) # Range 1 - min 120ns, increments of 30ns up to 983.13u # 2 - min 120ns, increments of 30.72us up to 1.007s # # F1TDC_CLOCK 0 <- Clock Source (0 = Internal 32 MHz) # (1 = External 31.25 MHz) # F1TDC_VERSION 2 <- Module Version (2 = High Resolution, synchronous, 32 channels) # (3 = Normal Resolution, synchronous, 48 channels) # set bin size from 0.056 to 0.058 -> Beni! # F1TDC_BIN_SIZE 0.058 <- Bin size (ns) # F1TDC_LATENCY 3000.0 <- Trigger latency (ns) # F1TDC_WINDOW 1000.0 <- Trigger window (ns) ========================== TRIGGER ========================== #CALIBRATION 1 TS_TRIG_TYPE 4 #TS_FP_INPUTS 9 10 #TS_FP_DELAY 9 24 #TS_FP_DELAY 10 50 TS_SOFT_TRIG 1 64000 0x1FFF 1 TS_TD_SLOTS 9 14 # SSP SLOT FIBER_EN SUM_ENABLE SSP_SLOT 9 0x8 1 SSP_SLOT 10 0 1 # TYPE DELAY INT_WIDTH ENABLE TRIG_EQ PS 35 10 0 TRIG_EQ BCAL_E 20 20 0 TRIG_EQ BCAL_C 20 10 0 TRIG_EQ FCAL 8 15 1 TRIG_EQ ST 20 10 0 TRIG_EQ TOF 20 10 0 # TRIG_EQ FCAL 8 15 1 # TYPE LATENCY WIDTH FCAL_E BCAL_E EN_THR NHIT LANE TRIG_TYPE PS 420 20 1300 1900 1100 0 -1 TRIG_TYPE BFCAL 452 20 0 1 58000 0 -1 TRIG_TYPE BFCAL 440 5 1 0 2000 0 0 TRIG_TYPE BCAL_COS 440 40 1500 2100 1300 0 -1 # TRIG_TYPE BFCAL 460 5 1 0 10000 0 0 TS_GTP_PRES 0 0 TS_TRIG_HOLD 1 1 TS_SYNC_INT 100 TRIG_DELAY 0 DAC_CALIB 0 TI_FIBER_LATENCY_OFFSET 0x98 TI_MASTER 0 TI_MASTER_TRIG 1 TI_FP_INPUTS 3 # TI_SOFT_TRIG 1 10000 0x7FFF 1 TI_SOFT_TRIG 1 10000 0x600 1 BLOCKLEVEL 10 BUFFERLEVEL 1 ========================== GLOBAL ========================== F1TDC_BIN_SIZE 0.058 ========================== FCAL ========================== FADC250_MODE 8 FADC250_W_OFFSET 820 FADC250_W_WIDTH 100 FADC250_NSB 3 FADC250_NSA 20 FADC250_NPEAK 3 FADC250_READ_THR 200 FADC250_TRIG_BL 100 FADC250_TRIG_THR 165 FADC250_TRIG_NSB 3 FADC250_TRIG_NSA 10 FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default FADC250_COM_VER default FADC250_USER_DIR /gluonfs1/gluex/CALIB/FCAL/fadc250/user/fall_2015 FADC250_USER_VER ring4_hot_v1 ========================== TABS ========================== FADC250_MODE 8 FADC250_W_OFFSET 800 FADC250_W_WIDTH 100 FADC250_NSB 3 FADC250_NSA 10 FADC250_NPEAK 1 FADC250_READ_THR 120 FADC250_TRIG_BL 100 FADC250_TRIG_THR 120 FADC250_TRIG_NSB 3 FADC250_TRIG_NSA 15 FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default FADC250_COM_VER default FADC250_USER_DIR FADC250_USER_VER # LE discriminator DSC2_WIDTH 40 40 DSC2_THRESHOLD 50 50 # CAEN 1290 TDC1290_W_WIDTH 3000 TDC1290_W_OFFSET -3000 TDC1290_W_EXTRA 25 TDC1290_W_REJECT 50 TDC1290_BLT_EVENTS 1 TDC1290_N_HITS 64 TDC1290_ALMOSTFULL 16384 TDC1290_OUT_PROG 2 TDC1290_A24_A32 2 TDC1290_SNGL_BLT 3 TDC1290_SST_RATE 0 TDC1290_BERR_FIFO 1 TDC1290_EDGE 2