#! Run type:: TRD Config:: TRG_BEAMLINE_PS_TRD_raw_b1.conf #! OUTPUT NAME:: /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/TRG_BEAMLINE_PS_TRD_raw_b1.conf #! (Re)Created:: on Wed Apr 13 11:20:33 EDT 2016 #! # # DSC2_WIDTH 20 40 <- TDC width (ns), TRG width (ns) # DSC2_THRESHOLD 20 50 <- board threshold: TDC threshold (mV), TRG threshold (mV) # # TS_TRIG_TYPE 1 - Internal Pulser # 2 - External FP # 4 - GTP # 6 - GTP + External # # # TS_FP_INPUTS - List of enabled FP inputs # # # TS_SOFT_TRIG # Trigger type (type 1 or 2 for playback) # Number of events to trigger # Period multiplier (depends on range 0-0x7FFF) # Range 1 - min 120ns, increments of 30ns up to 983.13u # 2 - min 120ns, increments of 30.72us up to 1.007s # # # TI_MASTER 1 - Stand alone with master TI # # TI_MASTER_TRIG 1 - soft, 2 - external pulser, 3 - playback # # TI_SOFT_TRIG # Trigger type (type 1 or 2 for playback) # Number of events to trigger # Period multiplier (depends on range 0-0x7FFF) # Range 1 - min 120ns, increments of 30ns up to 983.13u # 2 - min 120ns, increments of 30.72us up to 1.007s # # F1TDC_CLOCK 0 <- Clock Source (0 = Internal 32 MHz) # (1 = External 31.25 MHz) # F1TDC_VERSION 2 <- Module Version (2 = High Resolution, synchronous, 32 channels) # (3 = Normal Resolution, synchronous, 48 channels) # F1TDC_BIN_SIZE 0.056 <- Bin size (ns) # F1TDC_LATENCY 3000.0 <- Trigger latency (ns) # F1TDC_WINDOW 1000.0 <- Trigger window (ns) ========================== TRIGGER ========================== USE_PLAYBACK 0 #TS_TRIG_TYPE 1 TS_TRIG_TYPE 4 TS_FP_INPUTS 11 12 #TS_SOFT_TRIG 1 64000 0x7FF 1 TS_SOFT_TRIG 1 64000 0x1FF 1 TS_TD_SLOTS 3 14 # SSP SLOT FIBER_EN SUM_ENABLE SSP_SLOT 5 0x02 0 # TYPE DELAY INT_WIDTH ENABLE TRIG_EQ PS 20 10 1 TRIG_EQ BCAL_E 20 10 0 TRIG_EQ BCAL_C 20 10 0 TRIG_EQ FCAL 20 10 0 TRIG_EQ ST 20 10 0 TRIG_EQ TOF 20 10 0 # TYPE LATENCY WIDTH FCAL_E BCAL_E EN_THR NHIT LANE TRIG_TYPE PS 420 20 1300 1900 1100 0 0 TRIG_TYPE BFCAL 440 20 1 0 2000 0 -1 TRIG_TYPE BFCAL 440 20 1 0 1500 0 -1 TRIG_TYPE BCAL_COS 440 40 1500 2100 1300 0 -1 #TS_GTP_PRES 0 1 TRIG_DELAY 0 DAC_CALIB 0 TI_MASTER 0 TI_MASTER_TRIG 1 TI_FP_INPUTS 3 # TI_SOFT_TRIG 1 10000 0x7FFF 1 TI_SOFT_TRIG 1 10000 0x600 1 TI_FIBER_EN TS_TRIG_HOLD 62 1 BLOCKLEVEL 1 BUFFERLEVEL 1 # TI_FIBER_LATENCY_OFFSET 0xCA # TI_FIBER_LATENCY_OFFSET 0xA2 # TI_FIBER_LATENCY_OFFSET 0x89 # TI_FIBER_LATENCY_OFFSET 0x96 TI_FIBER_LATENCY_OFFSET 0x98 ========================== GLOBAL ========================== F1TDC_BIN_SIZE 0.058 ========================== TRD ========================== FADC125_MODE 7 FADC125_W_OFFSET 1010 FADC125_W_WIDTH 1000 FADC125_NSB 3 FADC125_NSA 12 FADC125_NPEAK 1 FADC125_THR 10 FADC125_DAC 36864 FA125_THRESHOLD_FACTOR 8 FADC125_COM_DIR /gluex/CALIB/ALL/fadc125/default FADC125_COM_VER default FADC125_USER_DIR /gluex/release/0.1/cdc/parms/common/fadc125 FADC125_USER_VER ------------------------------------------------------------------- # use file:: -rw-rw-r-- 1 hdops hdops 679 Feb 13 18:08 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/FCAL.master ========================== FCAL ========================== FADC250_MODE 8 FADC250_W_OFFSET 820 FADC250_W_WIDTH 100 FADC250_NSB 0 FADC250_NSA 15 FADC250_NPEAK 3 FADC250_READ_THR 108 #FADC250_READ_THR 125 FADC250_TRIG_BL 100 FADC250_TRIG_THR 165 FADC250_TRIG_NSB 3 FADC250_TRIG_NSA 10 FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default FADC250_COM_VER default #FADC250_USER_DIR /gluex/Subsystems/FCAL/FCAL_Analysis/DAQ/config #FADC250_USER_VER spring2015v2 FADC250_USER_DIR /gluonfs1/gluex/CALIB/FCAL/fadc250/user/fall_2015 FADC250_USER_VER ring4_hot_v1 ------------------------------------------------------------------- # use file:: -rw-rw-r-- 1 hdops hdops 1032 Mar 22 14:22 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/BCAL.master ========================== BCAL ========================== # change offset from 905 to 885 -> Beni 6.10.2014 afternoon # also change NSB and NSA from 3/6 to 5/40 FADC250_MODE 8 FADC250_W_OFFSET 825 FADC250_W_WIDTH 100 # Dalton: 2015-11-25 NSB -5->0 NSA 55->26 FADC250_NSB 2 FADC250_NSA 26 FADC250_NPEAK 3 # MMD threshold from 110 to 105 (2014-12-05) FADC250_READ_THR 105 FADC250_TRIG_BL 100 FADC250_TRIG_THR 120 FADC250_TRIG_NSB 3 FADC250_TRIG_NSA 19 FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default FADC250_COM_VER default FADC250_USER_DIR /gluex/CALIB/ALL/user FADC250_USER_VER SF1 #CTP_BCAL_THR 56000 #CTP_THR 10 # F1 TDC #change latency from 900. to 3540. and window from 500 to 1000 ->Beni F1TDC_WINDOW 1000. F1TDC_LATENCY 3400. # set bin size from 0.056 to 0.058 -> Beni! #F1TDC_BIN_SIZE 0.058 F1TDC_CLOCK 1 # LE discriminator DSC2_WIDTH 40 40 DSC2_THRESHOLD 35 50 ------------------------------------------------------------------- # use file:: -rw-rw-r-- 1 hdops hdops 1121 Feb 21 00:28 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/TOF.master ========================== TOF ========================== # change latency and width from 510/200 to 910/100 # and change NSB and NSA from 3/6 to 5/20 # btw. it is BENI # changed NSB & NSA from 5/20 to 10/45 (eugenio) FADC250_MODE 8 FADC250_W_OFFSET 810 FADC250_W_WIDTH 100 FADC250_NSB 0 FADC250_NSA 25 FADC250_NPEAK 3 FADC250_READ_THR 110 FADC250_TRIG_BL 100 FADC250_TRIG_THR 110 FADC250_TRIG_NSB 3 FADC250_TRIG_NSA 15 FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default FADC250_COM_VER default FADC250_USER_DIR /home/ FADC250_USER_VER #CTP_BCAL_THR 56000 # LE discriminator DSC2_WIDTH 20 40 DSC2_THRESHOLD 30 50 # CAEN 1290 #TDC1290_W_WIDTH 750 TDC1290_W_WIDTH 3800 #TDC1290_W_OFFSET -1750 #TDC1290_W_OFFSET -3640 TDC1290_W_OFFSET -3660 TDC1290_W_EXTRA 25 TDC1290_W_REJECT 50 TDC1290_BLT_EVENTS 1 TDC1290_N_HITS 64 TDC1290_ALMOSTFULL 16384 TDC1290_OUT_PROG 2 TDC1290_A24_A32 2 TDC1290_SNGL_BLT 3 TDC1290_SST_RATE 0 TDC1290_BERR_FIFO 1 TDC1290_EDGE 2 ------------------------------------------------------------------- # use file:: -rw-rw-r-- 1 hdops hdops 912 Feb 21 00:28 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/ST.master ========================== ST ========================== #change latency to 925 by BENI # also change NSA and NSB from 3/6 to 5/20 FADC250_MODE 8 FADC250_W_OFFSET 824 FADC250_W_WIDTH 100 FADC250_NSB 5 FADC250_NSA 20 FADC250_NPEAK 3 # change FADC250_READ_THR from 800 -> 110 by pooser (5 mV) # change FADC250_READ_THR from 110 -> 120 by pooser (10 mV) FADC250_READ_THR 120 FADC250_TRIG_BL 100 FADC250_TRIG_THR 130 FADC250_TRIG_NSB 3 FADC250_TRIG_NSA 15 FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default FADC250_COM_VER default FADC250_USER_DIR /home/ FADC250_USER_VER # F1 TDC # change latency from 2100 to 3700 F1TDC_WINDOW 1000. F1TDC_LATENCY 3460. F1TDC_CLOCK 1 # LE discriminator # change DSC2_THRESHOLD from 100 -> 50 by pooser DSC2_WIDTH 40 40 DSC2_THRESHOLD 50 60 ------------------------------------------------------------------- # use file:: -rw-rw-r-- 1 hdops hdops 699 Feb 21 00:29 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/TAGH.master ========================== TAGH ========================== FADC250_MODE 8 #FADC250_W_OFFSET 895 FADC250_W_OFFSET 905 FADC250_W_WIDTH 100 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 3 # changed from 120 to 300 FADC250_READ_THR 300 FADC250_TRIG_BL 100 FADC250_TRIG_THR 200 FADC250_TRIG_NSB 3 FADC250_TRIG_NSA 15 FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default FADC250_COM_VER default FADC250_USER_DIR /home/ FADC250_USER_VER CTP_USE 0 # F1 TDC F1TDC_WINDOW 600. F1TDC_LATENCY 3600. F1TDC_CLOCK 1 # LE discriminator DSC2_WIDTH 40 40 DSC2_THRESHOLD 45 45 ------------------------------------------------------------------- # use file:: -rw-rw-r-- 1 hdops hdops 1075 Mar 30 07:46 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/TAGM.master ========================== TAGM ========================== FADC250_MODE 8 #FADC250_W_OFFSET 895 FADC250_W_OFFSET 905 FADC250_W_WIDTH 100 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 3 # For low gain mode FADC250_READ_THR 115 # For high gain mode #FADC250_READ_THR 180 (changed 3/30/2016 for high-gain running RTJ) #FADC250_READ_THR 140 FADC250_TRIG_BL 100 FADC250_TRIG_THR 210 FADC250_TRIG_NSB 3 FADC250_TRIG_NSA 15 FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default FADC250_COM_VER default FADC250_USER_DIR /home/ FADC250_USER_VER CTP_USE 0 # F1 TDC F1TDC_WINDOW 600. F1TDC_LATENCY 3600. F1TDC_CLOCK 1 # LE discriminator # Change for high gain mode DSC2_WIDTH 40 40 #DSC2_THRESHOLD 10 60 #DSC2_THRESHOLD 20 20 DSC2_THRESHOLD 12 12 (changed 2/25/16 aebarnes) #DSC2_THRESHOLD 100 150 (changed 3/30/2016 for high-gain running RTJ) #DSC2_THRESHOLD 5 5 (changed for diamond alignment aebarnes 2/20/16) ------------------------------------------------------------------- # use file:: -rw-rw-r-- 1 hdops hdops 502 Feb 22 21:45 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/PS.master ========================== PS ========================== FADC250_MODE 8 FADC250_W_OFFSET 850 FADC250_W_WIDTH 100 FADC250_NSB 3 FADC250_NSA 10 FADC250_NPEAK 3 FADC250_READ_THR 130 FADC250_TRIG_BL 100 FADC250_TRIG_THR 200 FADC250_TRIG_NSB 3 FADC250_TRIG_NSA 15 FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default FADC250_COM_VER default FADC250_USER_DIR /home/somov/conf/cosmic FADC250_USER_VER ------------------------------------------------------------------- # use file:: -rw-rw-r-- 1 hdops hdops 502 Feb 21 00:44 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/PSC.master ========================== PSC ========================== FADC250_MODE 8 FADC250_W_OFFSET 850 FADC250_W_WIDTH 100 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 3 FADC250_READ_THR 150 FADC250_TRIG_BL 100 FADC250_TRIG_THR 150 FADC250_TRIG_NSB 3 FADC250_TRIG_NSA 6 # F1 TDC F1TDC_WINDOW 600. F1TDC_LATENCY 3540. F1TDC_CLOCK 1 # LE discriminator DSC2_WIDTH 40 40 DSC2_THRESHOLD 40 40 ------------------------------------------------------------------- # use file:: -rw-rw-r-- 1 hdops hdops 352 Feb 21 00:44 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/TPOL.master ========================== TPOL ========================== FADC250_MODE 8 FADC250_W_OFFSET 830 FADC250_W_WIDTH 100 FADC250_NSB 3 FADC250_NSA 6 FADC250_NPEAK 1 FADC250_READ_THR 133 FADC250_TRIG_BL 100 FADC250_TRIG_THR 500 FADC250_TRIG_NSB 3 FADC250_TRIG_NSA 6 ------------------------------------------------------------------- # use file:: -rw-rw-r-- 1 hdops hdops 713 Feb 8 23:07 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/CDC.master ========================== CDC ========================== # FADC125_MODE can be: # 3 = CDC_short 6 = CDC_long # 4 = FDC_short 7 = FDC_sum_long # 5 = FDC_amp_short 8 = FDC_amp_long FADC125_MODE 6 FADC125_W_OFFSET 425 FADC125_W_WIDTH 200 FADC125_IE 200 FADC125_NPEAK 1 FADC125_PG 4 FADC125_P1 4 FADC125_P2 4 FADC125_IBIT 4 FADC125_ABIT 3 FADC125_PBIT 0 FADC125_TH 100 FADC125_TL 25 FADC125_THR 500 FADC125_DAC 800 FADC125_COM_DIR /gluex/CALIB/ALL/fadc125/default FADC125_COM_VER default FADC125_USER_DIR /gluex/ FADC125_USER_VER ------------------------------------------------------------------- # use file:: -rw-rw-r-- 1 hdops hdops 1076 Mar 29 17:24 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/FDC.master ========================== FDC ========================== # FADC125_MODE can be: # 3 = CDC_short 6 = CDC_long # 4 = FDC_short 7 = FDC_sum_long # 5 = FDC_amp_short 8 = FDC_amp_long FADC125_MODE 8 FADC125_W_OFFSET 425 FADC125_W_WIDTH 100 FADC125_IE 16 FADC125_NPEAK 1 FADC125_PG 4 FADC125_P1 4 FADC125_P2 4 FADC125_IBIT 4 FADC125_ABIT 0 FADC125_PBIT 0 FADC125_TH 40 FADC125_TL 10 FADC125_THR 70 FADC125_DAC 800 FADC125_COM_DIR /gluex/CALIB/ALL/fadc125/default FADC125_COM_VER default FADC125_USER_DIR /gluex/ FADC125_USER_VER # F1 TDC # change latency and window back to what we expect from ADCs (Beni) F1TDC_WINDOW 1400. F1TDC_LATENCY 3560. #F1TDC_BIN_SIZE 0.112 # High-resolution board in slot 17 # changed by Beni (loser) 2014.10.6 F1TDC_HR_WINDOW 1000. F1TDC_HR_LATENCY 1160. # set bin size from 0.056 to 0.058 -> Beni! #F1TDC_HR_BIN_SIZE 0.058 F1TDC_CLOCK 1