Bug Summary

File:plugins/Utilities/evio_writer/DEventWriterEVIO.cc
Location:line 1177, column 14
Description:Value stored to 'buff_size' during its initialization is never read

Annotated Source Code

1#include "DEventWriterEVIO.h"
2#include "HDEVIOWriter.h"
3
4
5//file-scope so shared amongst threads; only accessed below via locks
6size_t gEVIONumOutputThreads = 0;
7map<string, HDEVIOWriter *>* gEVIOOutputters = NULL__null; // we own these writers
8map<string, pthread_t>* gEVIOOutputThreads = NULL__null;
9
10DEventWriterEVIO::DEventWriterEVIO(JEventLoop* locEventLoop)
11{
12 COMPACT = true;
13 PREFER_EMULATED = false;
14 DEBUG_FILES = false; // n.b. also defined in HDEVIOWriter
15
16 ofs_debug_input = NULL__null;
17 ofs_debug_output = NULL__null;
18
19 gPARMS->SetDefaultParameter("EVIOOUT:COMPACT" , COMPACT, "Drop words where we can to reduce output file size. This shouldn't loose any vital information, but can be turned off to help with debugging.");
20 gPARMS->SetDefaultParameter("EVIOOUT:PREFER_EMULATED" , PREFER_EMULATED, "If true, then sample data will not be written to output, but emulated hits will. Otherwise, do exactly the opposite.");
21 gPARMS->SetDefaultParameter("EVIOOUT:DEBUG_FILES" , DEBUG_FILES, "Write input and output debug files in addition to the standard output.");
22
23 // initialize file-level variables
24 japp->WriteLock("EVIOWriter");
25 {
26 ++gEVIONumOutputThreads;
27 if(gEVIOOutputters == NULL__null)
28 gEVIOOutputters = new map<string, HDEVIOWriter *>();
29 if(gEVIOOutputThreads == NULL__null)
30 gEVIOOutputThreads = new map<string, pthread_t>();
31 }
32 japp->Unlock("EVIOWriter");
33
34 if(DEBUG_FILES){
35 ofs_debug_input = new ofstream("hdevio_debug_input.evio");
36 if( !ofs_debug_input->is_open() ){
37 jerr << "Unable to open \"hdevio_debug_input.evio\"!" << endl;
38 delete ofs_debug_input;
39 ofs_debug_input = NULL__null;
40 }else{
41 jout << "Opened \"hdevio_debug_input.evio\" for debug output" << endl;
42 }
43
44 ofs_debug_output = new ofstream("hdevio_debug_output_preswap.evio");
45 if( !ofs_debug_output->is_open() ){
46 jerr << "Unable to open \"hdevio_debug_output_preswap.evio\"!" << endl;
47 delete ofs_debug_output;
48 ofs_debug_output = NULL__null;
49 }else{
50 jout << "Opened \"hdevio_debug_output_preswap.evio\" for debug output" << endl;
51 }
52 }
53}
54
55bool DEventWriterEVIO::Write_EVIOEvent(JEventLoop* locEventLoop, string locOutputFileNameSubString) const
56{
57 JEvent& locEvent = locEventLoop->GetJEvent();
58
59 // Get pointer to JEventSource and make sure it is the right type
60 JEventSource* locEventSource = locEvent.GetJEventSource();
61 if(locEventSource == NULL__null)
62 return false;
63
64#if !HAVE_EVIO1
65 jerr << "Compiled without EVIO! Cannot write event." << << endl;
66 return false;
67#endif // HAVE_EVIO
68
69 JEventSource_EVIO* locEvioSource = dynamic_cast<JEventSource_EVIO*>(locEventSource);
70 if(locEvioSource == NULL__null)
71 {
72 jerr << "WARNING!!! You MUST use this only with EVIO formatted data!!!" << endl;
73 return false;
74 }
75
76 // Optionally write input buffer to a debug file
77 if(DEBUG_FILES){
78 JEvent &jevent = locEventLoop->GetJEvent();
79 JEventSource *jes = jevent.GetJEventSource();
80 JEventSource_EVIO *jesevio = dynamic_cast<JEventSource_EVIO*>(jes);
81 if(!jesevio){
82 static bool warned = false;
83 if(!warned) jerr << "Event source not a JEventSource_EVIO type!" << endl;
84 warned = true;
85 }else{
86 uint32_t *buff;
87 uint32_t buff_size;
88 jesevio->GetEVIOBuffer(jevent, buff, buff_size);
89 if(ofs_debug_input) ofs_debug_input->write((char*)buff, buff_size*sizeof(uint32_t));
90 }
91 }
92
93 string locOutputFileName = Get_OutputFileName(locEventLoop, locOutputFileNameSubString);
94 japp->WriteLock("EVIOWriter");
95 {
96 //check to see if the EVIO file is open
97 if(gEVIOOutputters->find(locOutputFileName) == gEVIOOutputters->end())
98 {
99 //not open, open it
100 if(!Open_OutputFile(locEventLoop, locOutputFileName))
101 return false; //failed to open
102 }
103
104 //open: get handle, write event
105 HDEVIOWriter *locEVIOWriter = (*gEVIOOutputters)[locOutputFileName];
106 // Write event into buffer
107 vector<uint32_t> *buff = locEVIOWriter->GetBufferFromPool();
108 WriteEventToBuffer(locEventLoop, *buff);
109
110 // Optionally write buffer to output file
111 if(ofs_debug_output) ofs_debug_output->write((const char*)&(*buff)[0], buff->size()*sizeof(uint32_t));
112
113 // Add event to output queue
114 locEVIOWriter->AddBufferToOutput(buff);
115 }
116 japp->Unlock("EVIOWriter");
117
118 return true;
119}
120
121string DEventWriterEVIO::Get_OutputFileName(JEventLoop* locEventLoop, string locOutputFileNameSubString) const
122{
123 //get the event source
124 JEvent& locEvent = locEventLoop->GetJEvent();
125 JEventSource* locEventSource = locEvent.GetJEventSource();
126 if(locEventSource == NULL__null)
127 return "no_name.evio";
128
129 //get the source file name (strip the path)
130 string locSourceFileName = locEventSource->GetSourceName();
131 size_t locSlashIndex = locSourceFileName.find_last_of("/");
132 string locSourceFileName_Pathless = (locSlashIndex != string::npos) ? locSourceFileName.substr(locSlashIndex + 1) : locSourceFileName;
133
134 //strip the file extension (if present and if is a known format: .root, .evio, or .hddm)
135 size_t locDotIndex = locSourceFileName_Pathless.find_last_of(".");
136 if(locDotIndex != string::npos)
137 {
138 string locSuffix = locSourceFileName_Pathless.substr(locDotIndex + 1);
139 if((locSuffix == "root") || (locSuffix == "evio") || (locSuffix == "hddm"))
140 locSourceFileName_Pathless = locSourceFileName_Pathless.substr(0, locDotIndex);
141 }
142
143 return (locSourceFileName_Pathless + string(".") + locOutputFileNameSubString + string(".evio"));
144}
145
146bool DEventWriterEVIO::Open_OutputFile(JEventLoop* locEventLoop, string locOutputFileName) const
147{
148 //ASSUMES A LOCK HAS ALREADY BEEN ACQUIRED (by WriteEVIOEvent)
149 // and assume that it doesn't exist
150#if !HAVE_EVIO1
151 jerr << "Compiled without EVIO! Cannot open file:" << locOutputFileName << endl;
152 return false;
153#endif // HAVE_EVIO
154
155 // Create object to write the selected events to a file or ET system
156 // Run each connection in their own thread
157 HDEVIOWriter *locEVIOout = new HDEVIOWriter(locOutputFileName);
158 pthread_t locEVIOout_thr;
159 int result = pthread_create(&locEVIOout_thr, NULL__null, HDEVIOOutputThread, locEVIOout);
160 bool success = (result == 0);
161
162 //evaluate status
163 if(!success)
164 jerr << "Unable to open EVIO file: error code = " << result << endl;
165 else
166 {
167 jout << "Output EVIO file " << locOutputFileName << " created." << endl;
168 (*gEVIOOutputters)[locOutputFileName] = locEVIOout; //store the handle
169 (*gEVIOOutputThreads)[locOutputFileName] = locEVIOout_thr; //store the thread
170 }
171
172 return success;
173
174}
175
176DEventWriterEVIO::~DEventWriterEVIO(void)
177{
178#if HAVE_EVIO1
179 japp->WriteLock("EVIOWriter");
180 {
181 --gEVIONumOutputThreads;
182 if(gEVIONumOutputThreads > 0)
183 {
184 japp->Unlock("EVIOWriter");
185 return; //not the last thread writing to EVIO files
186 }
187
188 if(gEVIOOutputters == NULL__null)
189 {
190 japp->Unlock("EVIOWriter");
191 return; //not the last thread writing to EVIO files
192 }
193
194 //last thread writing to EVIO files: close all files and free all memory
195 map<string, HDEVIOWriter *>::iterator locIterator = gEVIOOutputters->begin();
196 for(; locIterator != gEVIOOutputters->end(); ++locIterator)
197 {
198 string locOutputFileName = locIterator->first;
199 HDEVIOWriter *locEVIOOutputter = locIterator->second;
200 pthread_t locEVIOOutputThread = (*gEVIOOutputThreads)[locOutputFileName];
201
202 // finish writing out to the event source
203 locEVIOOutputter->Quit();
204 // clean up the output thread
205 void *retval=NULL__null;
206 int result = pthread_join(locEVIOOutputThread, &retval);
207 if(result!=0)
208 jerr << "Problem closing EVIO file: error code = " << result << endl;
209 delete locEVIOOutputter;
210 std::cout << "Closed EVIO file " << locOutputFileName << std::endl;
211 }
212 delete gEVIOOutputters;
213 gEVIOOutputters = NULL__null;
214 delete gEVIOOutputThreads;
215 gEVIOOutputThreads = NULL__null;
216 }
217 japp->Unlock("EVIOWriter");
218#endif // HAVE_EVIO
219}
220
221//------------------
222// WriteEventToBuffer
223//------------------
224void DEventWriterEVIO::WriteEventToBuffer(JEventLoop *loop, vector<uint32_t> &buff) const
225{
226 /// This method will grab certain low-level objects and write them
227 /// into EVIO banks in a format compatible with the DAQ library.
228
229 // Handle BOR events separately
230 // These should only be at the beginning of a file or when the run changes
231 if( loop->GetJEvent().GetStatusBit(kSTATUS_BOR_EVENT) ){
232 WriteBORData(loop, buff);
233 return;
234 }
235
236 // First, grab all of the low level objects
237 vector<const Df250TriggerTime*> f250tts;
238 vector<const Df250PulseIntegral*> f250pis;
239 vector<const Df250WindowRawData*> f250wrds;
240 vector<const Df125TriggerTime*> f125tts;
241 vector<const Df125PulseIntegral*> f125pis;
242 vector<const Df125CDCPulse*> f125cdcpulses;
243 vector<const Df125FDCPulse*> f125fdcpulses;
244 vector<const Df125WindowRawData*> f125wrds;
245 vector<const Df125Config*> f125configs;
246 vector<const DCAEN1290TDCHit*> caen1290hits;
247 vector<const DCAEN1290TDCConfig*> caen1290configs;
248 vector<const DF1TDCHit*> F1hits;
249 vector<const DF1TDCTriggerTime*> F1tts;
250 vector<const DF1TDCConfig*> F1configs;
251 vector<const DEPICSvalue*> epicsValues;
252 vector<const DCODAEventInfo*> coda_events;
253 vector<const DCODAROCInfo*> coda_rocinfos;
254
255 loop->Get(f250tts);
256 loop->Get(f250pis);
257 loop->Get(f250wrds);
258 loop->Get(f125tts);
259 loop->Get(f125pis);
260 loop->Get(f125cdcpulses);
261 loop->Get(f125fdcpulses);
262 loop->Get(f125wrds);
263 loop->Get(f125configs);
264 loop->Get(caen1290hits);
265 loop->Get(caen1290configs);
266 loop->Get(F1hits);
267 loop->Get(F1tts);
268 loop->Get(F1configs);
269 loop->Get(epicsValues);
270 loop->Get(coda_events);
271 loop->Get(coda_rocinfos);
272
273 // Get the DL3Trigger object for the event. We go to some trouble
274 // here not to activate the factory ourselves and only check if the
275 // object already exists. This is because we may have skipped creating
276 // the object due to this being an unbiased event.
277 const DL3Trigger *l3trigger = NULL__null;
278 JFactory_base *fac = loop->GetFactory("DL3Trigger");
279 if(fac){
280 int nobjs = fac->GetNrows(false, true); // don't create objects if not already existing
281 if(nobjs>0){
282 loop->GetSingle(l3trigger, "", false); // don't throw exception if nobjs>1
283 }
284 }
285
286 // If there are any EPICS values then asume this is an EPICS event
287 // with no CODA data. In this case, write the EPICS banks and then
288 // return before writing the Physics Bank
289 if( !epicsValues.empty() ){
290 WriteEPICSData(buff, epicsValues);
291 return;
292 }
293
294 // Get list of rocids with hits
295 set<uint32_t> rocids;
296 rocids.insert(1); // This *may* be from TS (don't know). There is such a id in run 2391
297 for(uint32_t i=0; i<f250pis.size(); i++) rocids.insert( f250pis[i]->rocid );
298 for(uint32_t i=0; i<f250wrds.size(); i++) rocids.insert( f250wrds[i]->rocid );
299 for(uint32_t i=0; i<f125pis.size(); i++) rocids.insert( f125pis[i]->rocid );
300 for(uint32_t i=0; i<f125cdcpulses.size();i++) rocids.insert( f125cdcpulses[i]->rocid);
301 for(uint32_t i=0; i<f125fdcpulses.size();i++) rocids.insert( f125fdcpulses[i]->rocid);
302 for(uint32_t i=0; i<f125wrds.size(); i++) rocids.insert( f125wrds[i]->rocid );
303 for(uint32_t i=0; i<caen1290hits.size(); i++) rocids.insert( caen1290hits[i]->rocid );
304 for(uint32_t i=0; i<F1hits.size(); i++) rocids.insert( F1hits[i]->rocid );
305
306 // If COMPACT is true, filter coda_rocinfos to only have rocids with hits
307 if(COMPACT){
308 vector<const DCODAROCInfo*> my_coda_rocinfos;
309 for(uint32_t i=0; i<coda_rocinfos.size(); i++){
310 const DCODAROCInfo *rocinfo = coda_rocinfos[i];
311 if(rocids.find(coda_rocinfos[i]->rocid)!=rocids.end()){
312 my_coda_rocinfos.push_back(rocinfo);
313 }
314 }
315
316 // Replace coda_rocinfos with filtered list
317 coda_rocinfos = my_coda_rocinfos;
318 }
319
320 // Physics Bank Header
321 buff.clear();
322 buff.push_back(0); // Physics Event Length (must be updated at the end)
323 buff.push_back( 0xFF701001);// 0xFF70=SEB in single event mode, 0x10=bank of banks, 0x01=1event
324
325 // Built Trigger Bank
326 uint32_t built_trigger_bank_len_idx = buff.size();
327 buff.push_back(0); // Length
328 buff.push_back(0xFF232000 + coda_rocinfos.size()); // 0xFF23=Trigger Bank Tag, 0x20=segment
329
330 //--- Common Data Segments ---
331 // uint64_t segments for Event Number, avg. timestamp, Run Number, and Run Type
332 uint32_t run_number = loop->GetJEvent().GetRunNumber();
333 uint32_t run_type = 1; // observed in run 2931. Not sure shat it should be
334 uint64_t event_number = loop->GetJEvent().GetEventNumber();
335 uint64_t avg_timestamp = time(NULL__null);
336 if(!coda_events.empty()){
337 run_number = coda_events[0]->run_number;
338 run_type = coda_events[0]->run_type;
339 event_number = coda_events[0]->event_number;
340 avg_timestamp = coda_events[0]->avg_timestamp;
341 }
342
343 buff.push_back(0xD30A0006); // 0xD3=EB id (D3 stands for hallD level 3), 0x0A=64bit segment, 0006=length of segment (in 32bit words!)
344 buff.push_back(event_number & 0xFFFFFFFF); // low 32 bits of event number
345 buff.push_back(event_number>>32); // high 32 bits of event number
346 buff.push_back(avg_timestamp & 0xFFFFFFFF); // low 32 bits of avg. timestamp
347 buff.push_back(avg_timestamp>>32); // high 32 bits of avg. timestamp
348 //buff.push_back(run_number);
349 buff.push_back(run_type);
350 buff.push_back(run_number); // this is swapped from what one would expect (see JEventSource_EVIO::FindRunNumber()) - sdobbs (3/13/2016)
351
352 // uint16_t segment for Event Types
353 uint16_t event_type = 1; // observed in run 2931. Not sure what it should be
354 if(!coda_events.empty()){
355 event_type = coda_events[0]->event_type;
356 }
357 buff.push_back(0xD3850001); // 0xD3=EB id (D3 stands for hallD level 3), 0x85=16bit segment(8 is for padding), 0001=length of segment
358 buff.push_back((uint32_t)event_type);
359
360 unsigned int Nevents = loop->GetNevents();
361
362 //--- ROC Data ---
363 // uint32_t segments for ROC timestamp and misc. data
364 for(uint32_t i=0; i<coda_rocinfos.size(); i++){
365 const DCODAROCInfo *rocinfo = coda_rocinfos[i];
366
367 // Write ROC data for one roc
368 uint32_t len = 2 + rocinfo->misc.size(); // 2 = 2 words for 64bit timestamp
369 buff.push_back( (rocinfo->rocid<<24) + 0x00010000 + len); // 0x01=32bit segment
370 buff.push_back(rocinfo->timestamp & 0xFFFFFFFF); // low 32 bits of timestamp
371 buff.push_back(rocinfo->timestamp>>32); // high 32 bits of timestamp
372 if(!rocinfo->misc.empty()){
373 buff.insert(buff.end(), rocinfo->misc.begin(), rocinfo->misc.end()); // add all misc words
374 }
375 }
376
377 // Update Built trigger bank length
378 buff[built_trigger_bank_len_idx] = buff.size() - built_trigger_bank_len_idx - 1;
379
380 // Write EventTag
381 WriteEventTagData(buff, loop->GetJEvent().GetStatus(), l3trigger);
382
383 // Write CAEN1290TDC hits
384 WriteCAEN1290Data(buff, caen1290hits, caen1290configs, Nevents);
385
386 // Write F1TDC hits
387 WriteF1Data(buff, F1hits, F1tts, F1configs, Nevents);
388
389 // Write f250 hits
390 Writef250Data(buff, f250pis, f250tts, f250wrds, Nevents);
391
392 // Write f125 hits
393 Writef125Data(buff, f125pis, f125cdcpulses, f125fdcpulses, f125tts, f125wrds, f125configs, Nevents);
394
395 // Update global header length
396 if(!buff.empty()) buff[0] = buff.size()-1;
397}
398
399//------------------
400// WriteCAEN1290Data
401//------------------
402void DEventWriterEVIO::WriteCAEN1290Data(vector<uint32_t> &buff,
403 vector<const DCAEN1290TDCHit*> &caen1290hits,
404 vector<const DCAEN1290TDCConfig*> &caen1290configs,
405 unsigned int Nevents) const
406{
407 // Create lists of F1 hit objects indexed by rocid,slot
408 // At same time, make map of module types (32channel or 48 channel)
409 map<uint32_t, map<uint32_t, vector<const DCAEN1290TDCHit*> > > modules; // outer map index is rocid, inner map index is slot
410 map<uint32_t, set<const DCAEN1290TDCConfig*> > configs;
411 for(uint32_t i=0; i<caen1290hits.size(); i++){
412 const DCAEN1290TDCHit *hit = caen1290hits[i];
413 modules[hit->rocid][hit->slot].push_back(hit);
414 }
415
416 // Copy config pointers into map indexed by rocid
417 for(uint32_t i=0; i<caen1290configs.size(); i++){
418 const DCAEN1290TDCConfig *config = caen1290configs[i];
419 configs[config->rocid].insert(config);
420 }
421
422 // Loop over rocids
423 map<uint32_t, map<uint32_t, vector<const DCAEN1290TDCHit*> > >::iterator it;
424 for(it=modules.begin(); it!=modules.end(); it++){
425 uint32_t rocid = it->first;
426
427 // Write Physics Event's Data Bank Header for this rocid
428 uint32_t data_bank_idx = buff.size();
429 buff.push_back(0); // Total bank length (will be overwritten later)
430 buff.push_back( (rocid<<16) + 0x1001 ); // 0x10=bank of banks, 0x01=1 event
431
432 // Write Config Bank
433 set<const DCAEN1290TDCConfig*> &confs = configs[rocid];
434 if(!confs.empty()){
435
436 uint32_t config_bank_idx = buff.size();
437 buff.push_back(0); // Total bank length (will be overwritten later)
438 buff.push_back( 0x00550101 ); // 0x55=config bank, 0x01=uint32_t bank, 0x01=1 event
439
440 set<const DCAEN1290TDCConfig*>::iterator it_conf;
441 for(it_conf=confs.begin(); it_conf!=confs.end(); it_conf++){
442 const DCAEN1290TDCConfig *conf = *it_conf;
443
444 uint32_t header_idx = buff.size();
445 buff.push_back(0); // Nvals and slot mask (will be filled below)
446 uint32_t Nvals = 0; // keep count of how many params we write
447 if(conf->WINWIDTH != 0xFFFF) {buff.push_back( (kPARAMCAEN1290_WINWIDTH <<16) + conf->WINWIDTH ); Nvals++;}
448 if(conf->WINOFFSET != 0xFFFF) {buff.push_back( (kPARAMCAEN1290_WINOFFSET <<16) + conf->WINOFFSET ); Nvals++;}
449
450 buff[header_idx] = (Nvals<<24) + conf->slot_mask;
451 }
452
453 // Update Config Bank length
454 buff[config_bank_idx] = buff.size() - config_bank_idx - 1;
455 }
456
457 // Write Data Block Bank Header
458 uint32_t data_block_bank_idx = buff.size();
459 buff.push_back(0); // Total bank length (will be overwritten later)
460 buff.push_back( 0x00140101 ); // 0x00=status w/ little endian, 0x14=CAEN1290TDC, 0x01=uint32_t bank, 0x01=1 event
461
462 // Loop over slots
463 map<uint32_t, vector<const DCAEN1290TDCHit*> >::iterator it2;
464 for(it2=it->second.begin(); it2!=it->second.end(); it2++){
465 uint32_t slot = it2->first;
466
467 // Write global header
468 uint32_t global_header_idx = buff.size();
469 buff.push_back( 0x40000100 + (0x01<<5) + slot ); // Global Header 0x04=global header, 0x01<<5=event count
470
471 // Write module data
472 vector<const DCAEN1290TDCHit*> &hits = it2->second;
473 uint32_t last_id = 0x0;
474 for(uint32_t i=0; i<hits.size(); i++){
475 const DCAEN1290TDCHit *hit = hits[i];
476
477 // Check if we need to write a new TDC header
478 uint32_t id = (hit->tdc_num<<24) + (hit->event_id<<12) + (hit->bunch_id);
479 if(id != last_id){
480 // Write event header
481 buff.push_back( 0x08000000 + id ); // TDC Header
482 last_id = id;
483 }
484
485 // Write Hit
486 buff.push_back( (hit->edge<<26) + (hit->channel<<21) + (hit->time&0x1fffff) );
487 }
488
489 // Write module block trailer
490 uint32_t Nwords_in_block = buff.size()-global_header_idx+1;
491 buff.push_back( 0x80000000 + (Nwords_in_block<<5) + (slot) );
492 }
493
494 // Update Data Block Bank length
495 buff[data_block_bank_idx] = buff.size() - data_block_bank_idx - 1;
496
497 // Update Physics Event's Data Bank length
498 buff[data_bank_idx] = buff.size() - data_bank_idx - 1;
499 }
500}
501
502//------------------
503// WriteF1Data
504//------------------
505void DEventWriterEVIO::WriteF1Data(vector<uint32_t> &buff,
506 vector<const DF1TDCHit*> &F1hits,
507 vector<const DF1TDCTriggerTime*> &F1tts,
508 vector<const DF1TDCConfig*> &F1configs,
509 unsigned int Nevents) const
510{
511 // Create lists of F1 hit objects indexed by rocid,slot
512 // At same time, make map of module types (32channel or 48 channel)
513 map<uint32_t, map<uint32_t, vector<const DF1TDCHit*> > > modules; // outer map index is rocid, inner map index is slot
514 map<uint32_t, map<uint32_t, MODULE_TYPE> > mod_types;
515 for(uint32_t i=0; i<F1hits.size(); i++){
516 const DF1TDCHit *hit = F1hits[i];
517 modules[hit->rocid][hit->slot].push_back(hit);
518 mod_types[hit->rocid][hit->slot] = hit->modtype;
519 }
520
521 // Copy F1 config pointers into map indexed by rocid
522 map<uint32_t, set<const DF1TDCConfig*> > configs;
523 for(uint32_t i=0; i<F1configs.size(); i++){
524 const DF1TDCConfig *config = F1configs[i];
525 configs[config->rocid].insert(config);
526 }
527
528 // Loop over rocids
529 map<uint32_t, map<uint32_t, vector<const DF1TDCHit*> > >::iterator it;
530 for(it=modules.begin(); it!=modules.end(); it++){
531 uint32_t rocid = it->first;
532
533 // Write Physics Event's Data Bank Header for this rocid
534 uint32_t data_bank_idx = buff.size();
535 buff.push_back(0); // Total bank length (will be overwritten later)
536 buff.push_back( (rocid<<16) + 0x1001 ); // 0x10=bank of banks, 0x01=1 event
537
538 // Write Config Bank
539 set<const DF1TDCConfig*> &confs = configs[rocid];
540 if(!confs.empty()){
541
542 uint32_t config_bank_idx = buff.size();
543 buff.push_back(0); // Total bank length (will be overwritten later)
544 buff.push_back( 0x00550101 ); // 0x55=config bank, 0x01=uint32_t bank, 0x01=1 event
545
546 set<const DF1TDCConfig*>::iterator it_conf;
547 for(it_conf=confs.begin(); it_conf!=confs.end(); it_conf++){
548 const DF1TDCConfig *conf = *it_conf;
549
550 uint32_t header_idx = buff.size();
551 buff.push_back(0); // Nvals and slot mask (will be filled below)
552 uint32_t Nvals = 0; // keep count of how many params we write
553 if(conf->REFCNT != 0xFFFF) {buff.push_back( (kPARAMF1_REFCNT <<16) + conf->REFCNT ); Nvals++;}
554 if(conf->TRIGWIN != 0xFFFF) {buff.push_back( (kPARAMF1_TRIGWIN <<16) + conf->TRIGWIN ); Nvals++;}
555 if(conf->TRIGLAT != 0xFFFF) {buff.push_back( (kPARAMF1_TRIGLAT <<16) + conf->TRIGLAT ); Nvals++;}
556 if(conf->HSDIV != 0xFFFF) {buff.push_back( (kPARAMF1_HSDIV <<16) + conf->HSDIV ); Nvals++;}
557 if(conf->BINSIZE != 0xFFFF) {buff.push_back( (kPARAMF1_BINSIZE <<16) + conf->BINSIZE ); Nvals++;}
558 if(conf->REFCLKDIV != 0xFFFF) {buff.push_back( (kPARAMF1_REFCLKDIV <<16) + conf->REFCLKDIV ); Nvals++;}
559
560 buff[header_idx] = (Nvals<<24) + conf->slot_mask;
561 }
562
563 // Update Config Bank length
564 buff[config_bank_idx] = buff.size() - config_bank_idx - 1;
565 }
566
567 // Write Data Block Bank Header
568 // In principle, we could write one of these for each module, but
569 // we write all modules into the same data block bank to save space.
570 // n.b. the documentation mentions Single Event Mode (SEM) and that
571 // the values in the header and even the first couple of words depend
572 // on whether it is in that mode. It appears this mode is an alternative
573 // to having a Built Trigger Bank. Our data all seems to have been taken
574 // *not* in SEM. Empirically, it looks like the data also doesn't have
575 // the initial "Starting Event Number" though the documentation does not
576 // declare that as optional. We omit it here as well.
577 uint32_t data_block_bank_idx = buff.size();
578 buff.push_back(0); // Total bank length (will be overwritten later)
579 buff.push_back( 0x001A0101 ); // 0x00=status w/ little endian, 0x1A=F1TDC, 0x01=uint32_t bank, 0x01=1 event
580
581 // Loop over slots
582 map<uint32_t, vector<const DF1TDCHit*> >::iterator it2;
583 for(it2=it->second.begin(); it2!=it->second.end(); it2++){
584 uint32_t slot = it2->first;
585 MODULE_TYPE modtype = mod_types[rocid][slot];
586
587 // Find Trigger Time object
588 const DF1TDCTriggerTime *tt = NULL__null;
589 for(uint32_t i=0; i<F1tts.size(); i++){
590 if( (F1tts[i]->rocid==rocid) && (F1tts[i]->slot==slot) ){
591 tt = F1tts[i];
592 break;
593 }
594 }
595
596 // Set itrigger number and trigger time
597 uint32_t itrigger = (tt==NULL__null) ? (Nevents&0x3FFFFF):tt->DDAQAddress::itrigger;
598 uint64_t trig_time = (tt==NULL__null) ? time(NULL__null):tt->time;
599
600 // Write module block and event headers
601 uint32_t block_header_idx = buff.size();
602 buff.push_back( 0x80000101 + (modtype<<18) + (slot<<22) ); // Block Header 0x80=data defining, modtype=F1TDC, 0x01=event block number,0x01=number of events in block
603 buff.push_back( 0x90000000 + (slot<<22) + itrigger); // Event Header
604
605 // Write Trigger Time
606 buff.push_back(0x98000000 + ((trig_time>>0 )&0x00FFFFFF));
607 buff.push_back(0x00000000 + ((trig_time>>24)&0x00FFFFFF));
608
609 // Write module data
610 vector<const DF1TDCHit*> &hits = it2->second;
611 for(uint32_t i=0; i<hits.size(); i++){
612
613 // NOTE: We write out the chip header word here (data type 8)
614 // even though it contains mostly redundant information with the time
615 // measurement words written below. The primary exception is the
616 // 9bit "F1 Chip Trigger Time" value stored in the trig_time member
617 // of the DF1TDCHit object. This is not useful in the analysis other than
618 // to verify that separate chips on the module are in sync. To do this
619 // compactly, we would need to sort the list of hits by chip number as
620 // well so that we wrote one chip header for hits on that chip. That would
621 // make this more complicated and probably slower. Given
622 // that the original data contains lots of chip header words, even for
623 // chips with no hits, writing a header word per chip will still be more
624 // compact pretty much all of the time (unless there is really high occupancy
625 // in ALL F1TDC modules!)
626 // It may be worth noting that including this chip header does increase the
627 // output file size by about 3.5% for run 2931. We may want to consider
628 // only writing it when COMPACT=0 at some point since, as noted, it is not
629 // used anywhere in the reconstruction.
630 uint32_t data_word = hits[i]->data_word;
631 uint32_t chip_header = 0xC0000000;
632 chip_header += (data_word&0x07000000); // Resolution status, overflow statuses
633 chip_header += (hits[i]->trig_time<<7)&0x01FF; // 9bit trigger time
634 chip_header += (data_word>>16)&0x3F; // chip number and channel on chip
635 buff.push_back( chip_header );
636
637 // Write Hit
638 buff.push_back( data_word ); // original data word for F1 is conveniently recorded!
639 }
640
641 // Write module block trailer
642 uint32_t Nwords_in_block = buff.size()-block_header_idx+1;
643 buff.push_back( 0x88000000 + (slot<<22) + Nwords_in_block );
644 }
645
646 // Update Data Block Bank length
647 buff[data_block_bank_idx] = buff.size() - data_block_bank_idx - 1;
648
649 // Update Physics Event's Data Bank length
650 buff[data_bank_idx] = buff.size() - data_bank_idx - 1;
651 }
652}
653
654//------------------
655// Writef250Data
656//------------------
657void DEventWriterEVIO::Writef250Data(vector<uint32_t> &buff,
658 vector<const Df250PulseIntegral*> &f250pis,
659 vector<const Df250TriggerTime*> &f250tts,
660 vector<const Df250WindowRawData*> &f250wrds,
661 unsigned int Nevents) const
662{
663 // Create lists of Pulse Integral objects indexed by rocid,slot
664 // At same time, make list of config objects to write
665 map<uint32_t, map<uint32_t, vector<const Df250PulseIntegral*> > > modules; // outer map index is rocid, inner map index is slot
666 map<uint32_t, set<const Df250Config*> > configs;
667 for(uint32_t i=0; i<f250pis.size(); i++){
668 const Df250PulseIntegral *pi = f250pis[i];
669 modules[pi->rocid][pi->slot].push_back(pi);
670
671 const Df250Config *config = NULL__null;
672 pi->GetSingle(config);
673 if(config) configs[pi->rocid].insert(config);
674 }
675
676 // Make sure entries exist for all Df250WindowRawData objects as well
677 // so when we loop over rocid,slot below we can write those out under
678 // the appropriate block header.
679 for(uint32_t i=0; i<f250wrds.size(); i++) modules[f250wrds[i]->rocid][f250wrds[i]->slot];
680
681 // Loop over rocids
682 map<uint32_t, map<uint32_t, vector<const Df250PulseIntegral*> > >::iterator it;
683 for(it=modules.begin(); it!=modules.end(); it++){
684 uint32_t rocid = it->first;
685
686 // Write Physics Event's Data Bank Header for this rocid
687 uint32_t data_bank_idx = buff.size();
688 buff.push_back(0); // Total bank length (will be overwritten later)
689 buff.push_back( (rocid<<16) + 0x1001 ); // 0x10=bank of banks, 0x01=1 event
690
691 // Write Config Bank
692 set<const Df250Config*> &confs = configs[rocid];
693 if(!confs.empty()){
694
695 uint32_t config_bank_idx = buff.size();
696 buff.push_back(0); // Total bank length (will be overwritten later)
697 buff.push_back( 0x00550101 ); // 0x55=config bank, 0x01=uint32_t bank, 0x01=1 event
698
699 set<const Df250Config*>::iterator it_conf;
700 for(it_conf=confs.begin(); it_conf!=confs.end(); it_conf++){
701 const Df250Config *conf = *it_conf;
702
703 uint32_t header_idx = buff.size();
704 buff.push_back(0); // Nvals and slot mask (will be filled below)
705 uint32_t Nvals = 0; // keep count of how many params we write
706 if(conf->NSA != 0xFFFF) {buff.push_back( (kPARAM250_NSA <<16) + conf->NSA ); Nvals++;}
707 if(conf->NSB != 0xFFFF) {buff.push_back( (kPARAM250_NSB <<16) + conf->NSB ); Nvals++;}
708 if(conf->NSA_NSB != 0xFFFF) {buff.push_back( (kPARAM250_NSA_NSB<<16) + conf->NSA_NSB); Nvals++;}
709 if(conf->NPED != 0xFFFF) {buff.push_back( (kPARAM250_NPED <<16) + conf->NPED ); Nvals++;}
710
711 buff[header_idx] = (Nvals<<24) + conf->slot_mask;
712 }
713
714 // Update Config Bank length
715 buff[config_bank_idx] = buff.size() - config_bank_idx - 1;
716 }
717
718 // Write Data Block Bank Header
719 // In principle, we could write one of these for each module, but
720 // we write all modules into the same data block bank to save space.
721 // n.b. the documentation mentions Single Event Mode (SEM) and that
722 // the values in the header and even the first couple of words depend
723 // on whether it is in that mode. It appears this mode is an alternative
724 // to having a Built Trigger Bank. Our data all seems to have been taken
725 // *not* in SEM. Empirically, it looks like the data also doesn't have
726 // the initial "Starting Event Number" though the documentation does not
727 // declare that as optional. We omit it here as well.
728 uint32_t data_block_bank_idx = buff.size();
729 buff.push_back(0); // Total bank length (will be overwritten later)
730 buff.push_back(0x00060101); // 0x00=status w/ little endian, 0x06=f250, 0x01=uint32_t bank, 0x01=1 event
731
732 // Loop over slots
733 map<uint32_t, vector<const Df250PulseIntegral*> >::iterator it2;
734 for(it2=it->second.begin(); it2!=it->second.end(); it2++){
735 uint32_t slot = it2->first;
736
737 // Find Trigger Time object
738 const Df250TriggerTime *tt = NULL__null;
739 for(uint32_t i=0; i<f250tts.size(); i++){
740 if( (f250tts[i]->rocid==rocid) && (f250tts[i]->slot==slot) ){
741 tt = f250tts[i];
742 break;
743 }
744 }
745
746 // Should we print a warning if no Trigger Time object found?
747
748 // Set itrigger number and trigger time
749 uint32_t itrigger = (tt==NULL__null) ? (Nevents&0x3FFFFF):tt->itrigger;
750 uint64_t trig_time = (tt==NULL__null) ? time(NULL__null):tt->time;
751
752 // Write module block and event headers
753 uint32_t block_header_idx = buff.size();
754 buff.push_back( 0x80040101 + (slot<<22) ); // Block Header 0x80=data defining, 0x04=FADC250, 0x01=event block number,0x01=number of events in block
755 buff.push_back( 0x90000000 + (slot<<22) + itrigger); // Event Header
756
757 // Write Trigger Time
758 buff.push_back(0x98000000 + ((trig_time>>0 )&0x00FFFFFF));
759 buff.push_back(0x00000000 + ((trig_time>>24)&0x00FFFFFF));
760
761 // Write module data
762 vector<const Df250PulseIntegral*> &pis = it2->second;
763 for(uint32_t i=0; i<pis.size(); i++){
764 const Df250PulseIntegral *pi = pis[i];
765 const Df250PulseTime *pt = NULL__null;
766 const Df250PulsePedestal *pp = NULL__null;
767 pi->GetSingle(pt);
768 pi->GetSingle(pp);
769
770 // Pulse Integral
771 if(pi->emulated == PREFER_EMULATED){
772 buff.push_back(0xB8000000 + (pi->channel<<23) + (pi->pulse_number<<21) + (pi->quality_factor<<19) + (pi->integral&0x7FFFF) );
773 }
774
775 // Pulse Time
776 if(pt && (pt->emulated == PREFER_EMULATED) ){
777 buff.push_back(0xC0000000 + (pt->channel<<23) + (pt->pulse_number<<21) + (pt->quality_factor<<19) + (pt->time&0x7FFFF) );
778 }
779
780 // Pulse Pedestal
781 if(pp && (pp->emulated == PREFER_EMULATED) ){
782 buff.push_back(0xD0000000 + (pp->channel<<23) + (pp->pulse_number<<21) + (pp->pedestal<<12) + (pp->pulse_peak&0x0FFF) );
783 }
784 }
785
786 // Write Window Raw Data
787 // This is not the most efficient, but is needed to get these under
788 // the correct block header.
789 if(!PREFER_EMULATED){
790 for(uint32_t i=0; i<f250wrds.size(); i++){
791 const Df250WindowRawData *wrd = f250wrds[i];
792 if(wrd->rocid!=rocid || wrd->slot!=slot) continue;
793
794 // IMPORTANT: At this time, the individual "not valid" bits for
795 // the samples is not preserved in the Df250WindowRawData class.
796 // We set them here only to indicate if the last sample is not
797 // valid due to there being an odd number of samples.
798 buff.push_back(0xA0000000 + (wrd->channel<<23) + (wrd->samples.size()) );
799 for(uint32_t j=0; j<(wrd->samples.size()+1)/2; j++){
800 uint32_t idx1 = 2*j;
801 uint32_t idx2 = idx1 + 1;
802 uint32_t sample_1 = wrd->samples[idx1];
803 uint32_t sample_2 = idx2<wrd->samples.size() ? wrd->samples[idx2]:0;
804 uint32_t invalid1 = 0;
805 uint32_t invalid2 = idx2>=wrd->samples.size();
806 buff.push_back( (invalid1<<29) + (sample_1<<16) + (invalid2<<13) + (sample_2<<0) );
807 }
808 }
809 }
810
811 // Write module block trailer
812 uint32_t Nwords_in_block = buff.size()-block_header_idx+1;
813 buff.push_back( 0x88000000 + (slot<<22) + Nwords_in_block );
814 }
815
816 // Update Data Block Bank length
817 buff[data_block_bank_idx] = buff.size() - data_block_bank_idx - 1;
818
819 // Update Physics Event's Data Bank length
820 buff[data_bank_idx] = buff.size() - data_bank_idx - 1;
821 }
822}
823
824//------------------
825// Writef125Data
826//------------------
827void DEventWriterEVIO::Writef125Data(vector<uint32_t> &buff,
828 vector<const Df125PulseIntegral*> &f125pis,
829 vector<const Df125CDCPulse*> &f125cdcpulses,
830 vector<const Df125FDCPulse*> &f125fdcpulses,
831 vector<const Df125TriggerTime*> &f125tts,
832 vector<const Df125WindowRawData*> &f125wrds,
833 vector<const Df125Config*> &f125configs,
834 unsigned int Nevents) const
835{
836 // Make map of rocid,slot values that have some hit data.
837 // Simultaneously make map for each flavor of hit indexed by rocid,slot
838 map<uint32_t, set<uint32_t> > modules; // outer map index is rocid, inner map index is slot
839 map<uint32_t, map<uint32_t, vector<const Df125PulseIntegral*> > > pi_hits; // outer map index is rocid, inner map index is slot
840 map<uint32_t, map<uint32_t, vector<const Df125CDCPulse* > > > cdc_hits; // outer map index is rocid, inner map index is slot
841 map<uint32_t, map<uint32_t, vector<const Df125FDCPulse* > > > fdc_hits; // outer map index is rocid, inner map index is slot
842 map<uint32_t, map<uint32_t, vector<const Df125WindowRawData*> > > wrd_hits; // outer map index is rocid, inner map index is slot
843 for(uint32_t i=0; i<f125pis.size(); i++){
844 const Df125PulseIntegral *hit = f125pis[i];
845 modules[hit->rocid].insert(hit->slot);
846 pi_hits[hit->rocid][hit->slot].push_back( hit );
847 }
848 for(uint32_t i=0; i<f125cdcpulses.size(); i++){
849 const Df125CDCPulse *hit = f125cdcpulses[i];
850 modules[hit->rocid].insert(hit->slot);
851 cdc_hits[hit->rocid][hit->slot].push_back( hit );
852 }
853 for(uint32_t i=0; i<f125fdcpulses.size(); i++){
854 const Df125FDCPulse *hit = f125fdcpulses[i];
855 modules[hit->rocid].insert(hit->slot);
856 fdc_hits[hit->rocid][hit->slot].push_back( hit );
857 }
858 for(uint32_t i=0; i<f125wrds.size(); i++){
859 const Df125WindowRawData *hit = f125wrds[i];
860 modules[hit->rocid].insert(hit->slot);
861 wrd_hits[hit->rocid][hit->slot].push_back( hit );
862 }
863
864 // Copy f125 config pointers into map indexed by just rocid
865 map<uint32_t, set<const Df125Config*> > configs;
866 for(uint32_t i=0; i<f125configs.size(); i++){
867 const Df125Config *config = f125configs[i];
868 configs[config->rocid].insert(config);
869 }
870
871 // Loop over rocids
872 map<uint32_t, set<uint32_t> >::iterator it;
873 for(it=modules.begin(); it!=modules.end(); it++){
874 uint32_t rocid = it->first;
875
876 // Write Physics Event's Data Bank Header for this rocid
877 uint32_t data_bank_idx = buff.size();
878 buff.push_back(0); // Total bank length (will be overwritten later)
879 buff.push_back( (rocid<<16) + 0x1001 ); // 0x10=bank of banks, 0x01=1 event
880
881 // Write Config Bank
882 set<const Df125Config*> &confs = configs[rocid];
883 if(!confs.empty()){
884
885 uint32_t config_bank_idx = buff.size();
886 buff.push_back(0); // Total bank length (will be overwritten later)
887 buff.push_back( 0x00550101 ); // 0x55=config bank, 0x01=uint32_t bank, 0x01=1 event
888
889 set<const Df125Config*>::iterator it_conf;
890 for(it_conf=confs.begin(); it_conf!=confs.end(); it_conf++){
891 const Df125Config *conf = *it_conf;
892
893 uint32_t header_idx = buff.size();
894 buff.push_back(0); // Nvals and slot mask (will be filled below)
895 uint32_t Nvals = 0; // keep count of how many params we write
896 if(conf->NSA != 0xFFFF) {buff.push_back( (kPARAM125_NSA <<16) + conf->NSA ); Nvals++;}
897 if(conf->NSB != 0xFFFF) {buff.push_back( (kPARAM125_NSB <<16) + conf->NSB ); Nvals++;}
898 if(conf->NSA_NSB != 0xFFFF) {buff.push_back( (kPARAM125_NSA_NSB <<16) + conf->NSA_NSB ); Nvals++;}
899 if(conf->NPED != 0xFFFF) {buff.push_back( (kPARAM125_NPED <<16) + conf->NPED ); Nvals++;}
900 if(conf->WINWIDTH!= 0xFFFF) {buff.push_back( (kPARAM125_WINWIDTH<<16) + conf->WINWIDTH); Nvals++;}
901
902 // See GlueX-doc-2274
903 if(conf->PL != 0xFFFF) {buff.push_back( (kPARAM125_PL <<16) + conf->PL ); Nvals++;}
904 if(conf->NW != 0xFFFF) {buff.push_back( (kPARAM125_NW <<16) + conf->NW ); Nvals++;}
905 if(conf->NPK != 0xFFFF) {buff.push_back( (kPARAM125_NPK <<16) + conf->NPK ); Nvals++;}
906 if(conf->P1 != 0xFFFF) {buff.push_back( (kPARAM125_P1 <<16) + conf->P1 ); Nvals++;}
907 if(conf->P2 != 0xFFFF) {buff.push_back( (kPARAM125_P2 <<16) + conf->P2 ); Nvals++;}
908 if(conf->PG != 0xFFFF) {buff.push_back( (kPARAM125_PG <<16) + conf->PG ); Nvals++;}
909 if(conf->IE != 0xFFFF) {buff.push_back( (kPARAM125_IE <<16) + conf->IE ); Nvals++;}
910 if(conf->H != 0xFFFF) {buff.push_back( (kPARAM125_H <<16) + conf->H ); Nvals++;}
911 if(conf->TH != 0xFFFF) {buff.push_back( (kPARAM125_TH <<16) + conf->TH ); Nvals++;}
912 if(conf->TL != 0xFFFF) {buff.push_back( (kPARAM125_TL <<16) + conf->TL ); Nvals++;}
913 if(conf->IBIT != 0xFFFF) {buff.push_back( (kPARAM125_IBIT <<16) + conf->IBIT ); Nvals++;}
914 if(conf->ABIT != 0xFFFF) {buff.push_back( (kPARAM125_ABIT <<16) + conf->ABIT ); Nvals++;}
915 if(conf->PBIT != 0xFFFF) {buff.push_back( (kPARAM125_PBIT <<16) + conf->PBIT ); Nvals++;}
916
917 buff[header_idx] = (Nvals<<24) + conf->slot_mask;
918 }
919
920 // Update Config Bank length
921 buff[config_bank_idx] = buff.size() - config_bank_idx - 1;
922 }
923
924 // Write Data Block Bank Header
925 // In principle, we could write one of these for each module, but
926 // we write all modules into the same data block bank to save space.
927 // n.b. the documentation mentions Single Event Mode (SEM) and that
928 // the values in the header and even the first couple of words depend
929 // on whether it is in that mode. It appears this mode is an alternative
930 // to having a Built Trigger Bank. Our data all seems to have been taken
931 // *not* in SEM. Empirically, it looks like the data also doesn't have
932 // the initial "Starting Event Number" though the documentation does not
933 // declare that as optional. We omit it here as well.
934 uint32_t data_block_bank_idx = buff.size();
935 buff.push_back(0); // Total bank length (will be overwritten later)
936 buff.push_back(0x00100101); // 0x00=status w/ little endian, 0x10=f125, 0x01=uint32_t bank, 0x01=1 event
937
938 // Loop over slots
939 set<uint32_t>::iterator it2;
940 for(it2=it->second.begin(); it2!=it->second.end(); it2++){
941 uint32_t slot = *it2;
942
943 // Find Trigger Time object
944 const Df125TriggerTime *tt = NULL__null;
945 for(uint32_t i=0; i<f125tts.size(); i++){
946 if( (f125tts[i]->rocid==rocid) && (f125tts[i]->slot==slot) ){
947 tt = f125tts[i];
948 break;
949 }
950 }
951
952 // Should we print a warning if no Trigger Time object found?
953
954 // Set itrigger number and trigger time
955 uint32_t itrigger = (tt==NULL__null) ? (Nevents&0x3FFFFF):tt->DDAQAddress::itrigger;
956 uint64_t trig_time = (tt==NULL__null) ? time(NULL__null):tt->time;
957
958 // Write module block and event headers
959 uint32_t block_header_idx = buff.size();
960 buff.push_back( 0x80080101 + (slot<<22) ); // Block Header 0x80=data defining, 0x08=FADC125, 0x01=event block number,0x01=number of events in block
961 buff.push_back( 0x90000000 + itrigger); // Event Header
962
963 // Write Trigger Time
964 buff.push_back(0x98000000 + ((trig_time>>0 )&0x00FFFFFF));
965 buff.push_back(0x00000000 + ((trig_time>>24)&0x00FFFFFF));
966
967 // Write Pulse Integral (+Pedestal and Time) data
968 vector<const Df125PulseIntegral*> &pis = pi_hits[rocid][slot];
969 for(uint32_t i=0; i<pis.size(); i++){
970 const Df125PulseIntegral *pi = pis[i];
971 const Df125PulseTime *pt = NULL__null;
972 const Df125PulsePedestal *pp = NULL__null;
973 pi->GetSingle(pt);
974 pi->GetSingle(pp);
975
976 // Pulse Integral
977 if(pi->emulated == PREFER_EMULATED){
978 buff.push_back(0xB8000000 + (pi->channel<<20) + (pi->integral&0x7FFFF) );
979 }
980
981 // Pulse Time
982 if(pt && (pt->emulated == PREFER_EMULATED) ){
983 buff.push_back(0xC0000000 + (pt->channel<<20) + (pt->pulse_number<<18) + (pt->time&0x7FFFF) );
984 }
985
986 // Pulse Pedestal
987 if(pp && (pp->emulated == PREFER_EMULATED) ){
988 buff.push_back(0xD0000000 + (pp->pulse_number<<21) + (pp->pedestal<<12) + (pp->pulse_peak&0x0FFF) );
989 }
990 }
991
992 // Write CDC Pulse data
993 vector<const Df125CDCPulse*> &cdcpulses = cdc_hits[rocid][slot];
994 for(uint32_t i=0; i<cdcpulses.size(); i++){
995 const Df125CDCPulse *pulse = cdcpulses[i];
996
997 if(pulse->emulated == PREFER_EMULATED){
998 buff.push_back( pulse->word1 );
999 buff.push_back( pulse->word2 );
1000 }
1001 }
1002
1003 // Write FDC Pulse data
1004 vector<const Df125FDCPulse*> &fdcpulses = fdc_hits[rocid][slot];
1005 for(uint32_t i=0; i<fdcpulses.size(); i++){
1006 const Df125FDCPulse *pulse = fdcpulses[i];
1007
1008 if(pulse->emulated == PREFER_EMULATED){
1009 buff.push_back( pulse->word1 );
1010 buff.push_back( pulse->word2 );
1011 }
1012 }
1013
1014 // Write Window Raw Data
1015 // This is not the most efficient, but is needed to get these under
1016 // the correct block header.
1017 if(!PREFER_EMULATED){
1018 vector<const Df125WindowRawData*> &wrds = wrd_hits[rocid][slot];
1019 for(uint32_t i=0; i<wrds.size(); i++){
1020 const Df125WindowRawData *wrd = wrds[i];
1021
1022 // IMPORTANT: At this time, the individual "not valid" bits for
1023 // the samples is not preserved in the Df125WindowRawData class.
1024 // We set them here only to indicate if the last sample is not
1025 // valid due to there being an odd number of samples.
1026 buff.push_back(0xA0000000 + (wrd->channel<<20) + (wrd->channel<<15) + (wrd->samples.size()) );
1027 for(uint32_t j=0; j<(wrd->samples.size()+1)/2; j++){
1028 uint32_t idx1 = 2*j;
1029 uint32_t idx2 = idx1 + 1;
1030 uint32_t sample_1 = wrd->samples[idx1];
1031 uint32_t sample_2 = idx2<wrd->samples.size() ? wrd->samples[idx2]:0;
1032 uint32_t invalid1 = 0;
1033 uint32_t invalid2 = idx2>=wrd->samples.size();
1034 buff.push_back( (invalid1<<29) + (sample_1<<16) + (invalid2<<13) + (sample_2<<0) );
1035 }
1036 }
1037 }
1038
1039 // Write module block trailer
1040 uint32_t Nwords_in_block = buff.size()-block_header_idx+1;
1041 buff.push_back( 0x88000000 + (slot<<22) + Nwords_in_block );
1042 }
1043
1044 // Update Data Block Bank length
1045 buff[data_block_bank_idx] = buff.size() - data_block_bank_idx - 1;
1046
1047 // Update Physics Event's Data Bank length
1048 buff[data_bank_idx] = buff.size() - data_bank_idx - 1;
1049 }
1050}
1051
1052//------------------
1053// WriteEPICSData
1054//------------------
1055void DEventWriterEVIO::WriteEPICSData(vector<uint32_t> &buff,
1056 vector<const DEPICSvalue*> epicsValues) const
1057{
1058 // Store the EPICS event in EVIO as a bank of SEGMENTs
1059 // The first segment is a 32-bit unsigned int for the current
1060 // time. This is followed by additional SEGMENTs that are
1061 // 8-bit unsigned integer types, one for each variable being
1062 // written. All variables are written as strings in the form:
1063 //
1064 // varname=value
1065 //
1066 // where "varname" is the EPICS variable name and "value" its
1067 // value in string form. If there are multiple elements for
1068 // the PV, then value will be a comma separated list. The
1069 // contents of "value" are set in GetEPICSvalue() while
1070 // the "varname=value" string is formed here.
1071
1072 // If no values to write then return now
1073 if(epicsValues.size() == 0) return;
1074
1075 // Outermost EVIO header is a bank of segments.
1076 uint32_t epics_bank_idx = buff.size();
1077 buff.push_back(0); // Total bank length (will be overwritten later)
1078 buff.push_back( (0x60<<16) + (0xD<<8) + (0x1<<0) );
1079
1080 // Time word (unsigned 32bit SEGMENT)
1081 buff.push_back( (0x61<<24) + (0x1<<16) + (1<<0) );
1082 buff.push_back( (uint32_t)epicsValues[0]->timestamp );
1083
1084 // Loop over PVs, writing each as a SEGMENT to the buffer
1085 for(uint32_t i=0; i<epicsValues.size(); i++){
1086 const DEPICSvalue *epicsval = epicsValues[i];
1087 const string &str = epicsval->nameval;
1088 uint32_t Nbytes = str.size()+1; // +1 is for terminating 0
1089 uint32_t Nwords = (Nbytes+3)/4; // bytes needed for padding
1090 uint32_t Npad = (Nwords*4) - Nbytes;
1091
1092 buff.push_back( (0x62<<24) + (Npad<<22) + (0x7<<16) + (Nwords<<0) ); // 8bit unsigned char segment
1093
1094 // Increase buffer enough to hold this string
1095 uint32_t buff_str_idx = buff.size();
1096 buff.resize( buff_str_idx + Nwords );
1097
1098 unsigned char *ichar = (unsigned char*)&buff[buff_str_idx];
1099 for(unsigned int j=0; j<Nbytes; j++) ichar[j] = str[j]; // copy entire string including terminating 0
1100 }
1101
1102 // Update EPICS Bank length
1103 buff[epics_bank_idx] = buff.size() - epics_bank_idx - 1;
1104}
1105
1106//------------------
1107// WriteEventTagData
1108//------------------
1109void DEventWriterEVIO::WriteEventTagData(vector<uint32_t> &buff,
1110 uint64_t event_status,
1111 const DL3Trigger* l3trigger) const
1112{
1113 // Here we purposefully write the DEventTag data into a bank
1114 // based only on data extracted from other data objects, but
1115 // NOT the DEventTag object. This is so whenever an event is
1116 // written, it is guaranteed to have event tag data based on
1117 // current information as opposed to data passed in from a
1118 // previously run algorithm.
1119 uint32_t eventtag_bank_idx = buff.size();
1120
1121 uint64_t L3_status = 0;
1122 uint32_t L3_decision = 0;
1123 uint32_t L3_algorithm = 0;
1124 if(l3trigger){
1125 L3_status = l3trigger->status;
1126 L3_decision = l3trigger->L3_decision;
1127 L3_algorithm = l3trigger->algorithm;
1128 }
1129
1130 // Set L3 pass/fail status in event_status word to be written
1131 // (this is redundant with the L3_decision word written below
1132 // but makes the bits in the status word valid and costs nothing)
1133 switch(L3_decision){
1134 case DL3Trigger::kKEEP_EVENT : event_status |= kSTATUS_L3PASS; break;
1135 case DL3Trigger::kDISCARD_EVENT: event_status |= kSTATUS_L3FAIL; break;
1136 case DL3Trigger::kNO_DECISION : break;
1137 }
1138
1139 // Length and Header words
1140 buff.push_back(0); // Total bank length (will be overwritten later)
1141 buff.push_back( 0x00560101 ); // 0x56=event tag bank, 0x01=uint32_t bank, 0x01=1 event
1142
1143 // event_status
1144 buff.push_back( (event_status>> 0)&0xFFFFFFFF ); // low order word
1145 buff.push_back( (event_status>>32)&0xFFFFFFFF ); // high order word
1146
1147 // L3_status
1148 buff.push_back( (L3_status>> 0)&0xFFFFFFFF ); // low order word
1149 buff.push_back( (L3_status>>32)&0xFFFFFFFF ); // high order word
1150
1151 // L3_decision
1152 buff.push_back( L3_decision );
1153
1154 // L3_algorithm
1155 buff.push_back( L3_algorithm );
1156
1157 // Update event tag Bank length
1158 buff[eventtag_bank_idx] = buff.size() - eventtag_bank_idx - 1;
1159}
1160
1161
1162//------------------
1163// WriteBORData
1164//------------------
1165void DEventWriterEVIO::WriteBORData(JEventLoop *loop, vector<uint32_t> &buff) const
1166{
1167 // The Begin-Of-Run (BOR) record is a special record that should show up
1168 // at the beginning of each EVIO file and any time a new run starts during a file
1169 // We want to preserve its format, so the easiest way to handle it is just to copy
1170 // it straight to the output. It's always (so far) saved as a single event,
1171 // consisting of a bank of banks of config information
1172
1173 // grab buffer corresponding to this event
1174 // note that we get everything after the EVIO block header
1175 void *ref = loop->GetJEvent().GetRef();
1176 uint32_t *in_buff = JEventSource_EVIO::GetEVIOBufferFromRef(ref);
1177 uint32_t buff_size = JEventSource_EVIO::GetEVIOBufferSizeFromRef(ref); // this is much larger than the bank size - not sure why
Value stored to 'buff_size' during its initialization is never read
1178
1179 uint32_t Nwords = in_buff[0]; // number of words in BOR config bank
1180 // copy entire bank
1181 for(uint32_t i=0; i<Nwords+1; i++) buff.push_back( in_buff[i] );
1182
1183}