Bug Summary

File:plugins/Utilities/evio_writer/DEventWriterEVIO.cc
Location:line 1178, column 14
Description:Value stored to 'buff_size' during its initialization is never read

Annotated Source Code

1#include "DEventWriterEVIO.h"
2
3size_t& DEventWriterEVIO::Get_NumEVIOOutputThreads(void) const
4{
5 // must be read/used entirely in "EVIOWriter" lock
6 static size_t locEVIONumOutputThreads = 0;
7 return locEVIONumOutputThreads;
8}
9
10map<string, HDEVIOWriter*>& DEventWriterEVIO::Get_EVIOOutputters(void) const
11{
12 // must be read/used entirely in "EVIOWriter" lock
13 static map<string, HDEVIOWriter*> locEVIOOutputters;
14 return locEVIOOutputters;
15}
16
17map<string, pthread_t>& DEventWriterEVIO::Get_EVIOOutputThreads(void) const
18{
19 // must be read/used entirely in "EVIOWriter" lock
20 static map<string, pthread_t> locEVIOOutputThreads;
21 return locEVIOOutputThreads;
22}
23
24DEventWriterEVIO::DEventWriterEVIO(JEventLoop* locEventLoop)
25{
26 COMPACT = true;
27 PREFER_EMULATED = false;
28 DEBUG_FILES = false; // n.b. also defined in HDEVIOWriter
29
30 ofs_debug_input = NULL__null;
31 ofs_debug_output = NULL__null;
32
33 gPARMS->SetDefaultParameter("EVIOOUT:COMPACT" , COMPACT, "Drop words where we can to reduce output file size. This shouldn't loose any vital information, but can be turned off to help with debugging.");
34 gPARMS->SetDefaultParameter("EVIOOUT:PREFER_EMULATED" , PREFER_EMULATED, "If true, then sample data will not be written to output, but emulated hits will. Otherwise, do exactly the opposite.");
35 gPARMS->SetDefaultParameter("EVIOOUT:DEBUG_FILES" , DEBUG_FILES, "Write input and output debug files in addition to the standard output.");
36
37 // initialize file-level variables
38 japp->WriteLock("EVIOWriter");
39 {
40 ++Get_NumEVIOOutputThreads();
41 }
42 japp->Unlock("EVIOWriter");
43
44 if(DEBUG_FILES){
45 ofs_debug_input = new ofstream("hdevio_debug_input.evio");
46 if( !ofs_debug_input->is_open() ){
47 jerr << "Unable to open \"hdevio_debug_input.evio\"!" << endl;
48 delete ofs_debug_input;
49 ofs_debug_input = NULL__null;
50 }else{
51 jout << "Opened \"hdevio_debug_input.evio\" for debug output" << endl;
52 }
53
54 ofs_debug_output = new ofstream("hdevio_debug_output_preswap.evio");
55 if( !ofs_debug_output->is_open() ){
56 jerr << "Unable to open \"hdevio_debug_output_preswap.evio\"!" << endl;
57 delete ofs_debug_output;
58 ofs_debug_output = NULL__null;
59 }else{
60 jout << "Opened \"hdevio_debug_output_preswap.evio\" for debug output" << endl;
61 }
62 }
63}
64
65bool DEventWriterEVIO::Write_EVIOEvent(JEventLoop* locEventLoop, string locOutputFileNameSubString) const
66{
67 JEvent& locEvent = locEventLoop->GetJEvent();
68
69 // Get pointer to JEventSource and make sure it is the right type
70 JEventSource* locEventSource = locEvent.GetJEventSource();
71 if(locEventSource == NULL__null)
72 return false;
73
74#if !HAVE_EVIO1
75 jerr << "Compiled without EVIO! Cannot write event." << << endl;
76 return false;
77#endif // HAVE_EVIO
78
79 JEventSource_EVIO* locEvioSource = dynamic_cast<JEventSource_EVIO*>(locEventSource);
80 if(locEvioSource == NULL__null)
81 {
82 jerr << "WARNING!!! You MUST use this only with EVIO formatted data!!!" << endl;
83 return false;
84 }
85
86 // Optionally write input buffer to a debug file
87 if(DEBUG_FILES){
88 JEvent &jevent = locEventLoop->GetJEvent();
89 JEventSource *jes = jevent.GetJEventSource();
90 JEventSource_EVIO *jesevio = dynamic_cast<JEventSource_EVIO*>(jes);
91 if(!jesevio){
92 static bool warned = false;
93 if(!warned) jerr << "Event source not a JEventSource_EVIO type!" << endl;
94 warned = true;
95 }else{
96 uint32_t *buff;
97 uint32_t buff_size;
98 jesevio->GetEVIOBuffer(jevent, buff, buff_size);
99 if(ofs_debug_input) ofs_debug_input->write((char*)buff, buff_size*sizeof(uint32_t));
100 }
101 }
102
103 string locOutputFileName = Get_OutputFileName(locEventLoop, locOutputFileNameSubString);
104 japp->WriteLock("EVIOWriter");
105 {
106 //check to see if the EVIO file is open
107 if(Get_EVIOOutputters().find(locOutputFileName) == Get_EVIOOutputters().end())
108 {
109 //not open, open it
110 if(!Open_OutputFile(locEventLoop, locOutputFileName))
111 return false; //failed to open
112 }
113
114 //open: get handle, write event
115 HDEVIOWriter *locEVIOWriter = Get_EVIOOutputters()[locOutputFileName];
116 // Write event into buffer
117 vector<uint32_t> *buff = locEVIOWriter->GetBufferFromPool();
118 WriteEventToBuffer(locEventLoop, *buff);
119
120 // Optionally write buffer to output file
121 if(ofs_debug_output) ofs_debug_output->write((const char*)&(*buff)[0], buff->size()*sizeof(uint32_t));
122
123 // Add event to output queue
124 locEVIOWriter->AddBufferToOutput(buff);
125 }
126 japp->Unlock("EVIOWriter");
127
128 return true;
129}
130
131string DEventWriterEVIO::Get_OutputFileName(JEventLoop* locEventLoop, string locOutputFileNameSubString) const
132{
133 //get the event source
134 JEvent& locEvent = locEventLoop->GetJEvent();
135 JEventSource* locEventSource = locEvent.GetJEventSource();
136 if(locEventSource == NULL__null)
137 return "no_name.evio";
138
139 //get the source file name (strip the path)
140 string locSourceFileName = locEventSource->GetSourceName();
141 size_t locSlashIndex = locSourceFileName.find_last_of("/");
142 string locSourceFileName_Pathless = (locSlashIndex != string::npos) ? locSourceFileName.substr(locSlashIndex + 1) : locSourceFileName;
143
144 //strip the file extension (if present and if is a known format: .root, .evio, or .hddm)
145 size_t locDotIndex = locSourceFileName_Pathless.find_last_of(".");
146 if(locDotIndex != string::npos)
147 {
148 string locSuffix = locSourceFileName_Pathless.substr(locDotIndex + 1);
149 if((locSuffix == "root") || (locSuffix == "evio") || (locSuffix == "hddm"))
150 locSourceFileName_Pathless = locSourceFileName_Pathless.substr(0, locDotIndex);
151 }
152
153 return (locSourceFileName_Pathless + string(".") + locOutputFileNameSubString + string(".evio"));
154}
155
156bool DEventWriterEVIO::Open_OutputFile(JEventLoop* locEventLoop, string locOutputFileName) const
157{
158 //ASSUMES A LOCK HAS ALREADY BEEN ACQUIRED (by WriteEVIOEvent)
159 // and assume that it doesn't exist
160#if !HAVE_EVIO1
161 jerr << "Compiled without EVIO! Cannot open file:" << locOutputFileName << endl;
162 return false;
163#endif // HAVE_EVIO
164
165 // Create object to write the selected events to a file or ET system
166 // Run each connection in their own thread
167 HDEVIOWriter *locEVIOout = new HDEVIOWriter(locOutputFileName);
168 pthread_t locEVIOout_thr;
169 int result = pthread_create(&locEVIOout_thr, NULL__null, HDEVIOOutputThread, locEVIOout);
170 bool success = (result == 0);
171
172 //evaluate status
173 if(!success)
174 jerr << "Unable to open EVIO file: error code = " << result << endl;
175 else
176 {
177 jout << "Output EVIO file " << locOutputFileName << " created." << endl;
178 Get_EVIOOutputters()[locOutputFileName] = locEVIOout; //store the handle
179 Get_EVIOOutputThreads()[locOutputFileName] = locEVIOout_thr; //store the thread
180 }
181
182 return success;
183}
184
185DEventWriterEVIO::~DEventWriterEVIO(void)
186{
187#if HAVE_EVIO1
188 japp->WriteLock("EVIOWriter");
189 {
190 --Get_NumEVIOOutputThreads();
191 if(Get_NumEVIOOutputThreads() > 0)
192 {
193 japp->Unlock("EVIOWriter");
194 return; //not the last thread writing to EVIO files
195 }
196
197 //last thread writing to EVIO files: close all files and free all memory
198 map<string, HDEVIOWriter *>::iterator locIterator = Get_EVIOOutputters().begin();
199 for(; locIterator != Get_EVIOOutputters().end(); ++locIterator)
200 {
201 string locOutputFileName = locIterator->first;
202 HDEVIOWriter *locEVIOOutputter = locIterator->second;
203 pthread_t locEVIOOutputThread = Get_EVIOOutputThreads()[locOutputFileName];
204
205 // finish writing out to the event source
206 locEVIOOutputter->Quit();
207 // clean up the output thread
208 void *retval=NULL__null;
209 int result = pthread_join(locEVIOOutputThread, &retval);
210 if(result!=0)
211 jerr << "Problem closing EVIO file: error code = " << result << endl;
212 delete locEVIOOutputter;
213 std::cout << "Closed EVIO file " << locOutputFileName << std::endl;
214 }
215 Get_EVIOOutputters().clear();
216 Get_EVIOOutputThreads().clear();
217 }
218 japp->Unlock("EVIOWriter");
219#endif // HAVE_EVIO
220}
221
222//------------------
223// WriteEventToBuffer
224//------------------
225void DEventWriterEVIO::WriteEventToBuffer(JEventLoop *loop, vector<uint32_t> &buff) const
226{
227 /// This method will grab certain low-level objects and write them
228 /// into EVIO banks in a format compatible with the DAQ library.
229
230 // Handle BOR events separately
231 // These should only be at the beginning of a file or when the run changes
232 if( loop->GetJEvent().GetStatusBit(kSTATUS_BOR_EVENT) ){
233 WriteBORData(loop, buff);
234 return;
235 }
236
237 // First, grab all of the low level objects
238 vector<const Df250TriggerTime*> f250tts;
239 vector<const Df250PulseIntegral*> f250pis;
240 vector<const Df250WindowRawData*> f250wrds;
241 vector<const Df125TriggerTime*> f125tts;
242 vector<const Df125PulseIntegral*> f125pis;
243 vector<const Df125CDCPulse*> f125cdcpulses;
244 vector<const Df125FDCPulse*> f125fdcpulses;
245 vector<const Df125WindowRawData*> f125wrds;
246 vector<const Df125Config*> f125configs;
247 vector<const DCAEN1290TDCHit*> caen1290hits;
248 vector<const DCAEN1290TDCConfig*> caen1290configs;
249 vector<const DF1TDCHit*> F1hits;
250 vector<const DF1TDCTriggerTime*> F1tts;
251 vector<const DF1TDCConfig*> F1configs;
252 vector<const DEPICSvalue*> epicsValues;
253 vector<const DCODAEventInfo*> coda_events;
254 vector<const DCODAROCInfo*> coda_rocinfos;
255
256 loop->Get(f250tts);
257 loop->Get(f250pis);
258 loop->Get(f250wrds);
259 loop->Get(f125tts);
260 loop->Get(f125pis);
261 loop->Get(f125cdcpulses);
262 loop->Get(f125fdcpulses);
263 loop->Get(f125wrds);
264 loop->Get(f125configs);
265 loop->Get(caen1290hits);
266 loop->Get(caen1290configs);
267 loop->Get(F1hits);
268 loop->Get(F1tts);
269 loop->Get(F1configs);
270 loop->Get(epicsValues);
271 loop->Get(coda_events);
272 loop->Get(coda_rocinfos);
273
274 // Get the DL3Trigger object for the event. We go to some trouble
275 // here not to activate the factory ourselves and only check if the
276 // object already exists. This is because we may have skipped creating
277 // the object due to this being an unbiased event.
278 const DL3Trigger *l3trigger = NULL__null;
279 JFactory_base *fac = loop->GetFactory("DL3Trigger");
280 if(fac){
281 int nobjs = fac->GetNrows(false, true); // don't create objects if not already existing
282 if(nobjs>0){
283 loop->GetSingle(l3trigger, "", false); // don't throw exception if nobjs>1
284 }
285 }
286
287 // If there are any EPICS values then asume this is an EPICS event
288 // with no CODA data. In this case, write the EPICS banks and then
289 // return before writing the Physics Bank
290 if( !epicsValues.empty() ){
291 WriteEPICSData(buff, epicsValues);
292 return;
293 }
294
295 // Get list of rocids with hits
296 set<uint32_t> rocids;
297 rocids.insert(1); // This *may* be from TS (don't know). There is such a id in run 2391
298 for(uint32_t i=0; i<f250pis.size(); i++) rocids.insert( f250pis[i]->rocid );
299 for(uint32_t i=0; i<f250wrds.size(); i++) rocids.insert( f250wrds[i]->rocid );
300 for(uint32_t i=0; i<f125pis.size(); i++) rocids.insert( f125pis[i]->rocid );
301 for(uint32_t i=0; i<f125cdcpulses.size();i++) rocids.insert( f125cdcpulses[i]->rocid);
302 for(uint32_t i=0; i<f125fdcpulses.size();i++) rocids.insert( f125fdcpulses[i]->rocid);
303 for(uint32_t i=0; i<f125wrds.size(); i++) rocids.insert( f125wrds[i]->rocid );
304 for(uint32_t i=0; i<caen1290hits.size(); i++) rocids.insert( caen1290hits[i]->rocid );
305 for(uint32_t i=0; i<F1hits.size(); i++) rocids.insert( F1hits[i]->rocid );
306
307 // If COMPACT is true, filter coda_rocinfos to only have rocids with hits
308 if(COMPACT){
309 vector<const DCODAROCInfo*> my_coda_rocinfos;
310 for(uint32_t i=0; i<coda_rocinfos.size(); i++){
311 const DCODAROCInfo *rocinfo = coda_rocinfos[i];
312 if(rocids.find(coda_rocinfos[i]->rocid)!=rocids.end()){
313 my_coda_rocinfos.push_back(rocinfo);
314 }
315 }
316
317 // Replace coda_rocinfos with filtered list
318 coda_rocinfos = my_coda_rocinfos;
319 }
320
321 // Physics Bank Header
322 buff.clear();
323 buff.push_back(0); // Physics Event Length (must be updated at the end)
324 buff.push_back( 0xFF701001);// 0xFF70=SEB in single event mode, 0x10=bank of banks, 0x01=1event
325
326 // Built Trigger Bank
327 uint32_t built_trigger_bank_len_idx = buff.size();
328 buff.push_back(0); // Length
329 buff.push_back(0xFF232000 + coda_rocinfos.size()); // 0xFF23=Trigger Bank Tag, 0x20=segment
330
331 //--- Common Data Segments ---
332 // uint64_t segments for Event Number, avg. timestamp, Run Number, and Run Type
333 uint32_t run_number = loop->GetJEvent().GetRunNumber();
334 uint32_t run_type = 1; // observed in run 2931. Not sure shat it should be
335 uint64_t event_number = loop->GetJEvent().GetEventNumber();
336 uint64_t avg_timestamp = time(NULL__null);
337 if(!coda_events.empty()){
338 run_number = coda_events[0]->run_number;
339 run_type = coda_events[0]->run_type;
340 event_number = coda_events[0]->event_number;
341 avg_timestamp = coda_events[0]->avg_timestamp;
342 }
343
344 buff.push_back(0xD30A0006); // 0xD3=EB id (D3 stands for hallD level 3), 0x0A=64bit segment, 0006=length of segment (in 32bit words!)
345 buff.push_back(event_number & 0xFFFFFFFF); // low 32 bits of event number
346 buff.push_back(event_number>>32); // high 32 bits of event number
347 buff.push_back(avg_timestamp & 0xFFFFFFFF); // low 32 bits of avg. timestamp
348 buff.push_back(avg_timestamp>>32); // high 32 bits of avg. timestamp
349 //buff.push_back(run_number);
350 buff.push_back(run_type);
351 buff.push_back(run_number); // this is swapped from what one would expect (see JEventSource_EVIO::FindRunNumber()) - sdobbs (3/13/2016)
352
353 // uint16_t segment for Event Types
354 uint16_t event_type = 1; // observed in run 2931. Not sure what it should be
355 if(!coda_events.empty()){
356 event_type = coda_events[0]->event_type;
357 }
358 buff.push_back(0xD3850001); // 0xD3=EB id (D3 stands for hallD level 3), 0x85=16bit segment(8 is for padding), 0001=length of segment
359 buff.push_back((uint32_t)event_type);
360
361 unsigned int Nevents = loop->GetNevents();
362
363 //--- ROC Data ---
364 // uint32_t segments for ROC timestamp and misc. data
365 for(uint32_t i=0; i<coda_rocinfos.size(); i++){
366 const DCODAROCInfo *rocinfo = coda_rocinfos[i];
367
368 // Write ROC data for one roc
369 uint32_t len = 2 + rocinfo->misc.size(); // 2 = 2 words for 64bit timestamp
370 buff.push_back( (rocinfo->rocid<<24) + 0x00010000 + len); // 0x01=32bit segment
371 buff.push_back(rocinfo->timestamp & 0xFFFFFFFF); // low 32 bits of timestamp
372 buff.push_back(rocinfo->timestamp>>32); // high 32 bits of timestamp
373 if(!rocinfo->misc.empty()){
374 buff.insert(buff.end(), rocinfo->misc.begin(), rocinfo->misc.end()); // add all misc words
375 }
376 }
377
378 // Update Built trigger bank length
379 buff[built_trigger_bank_len_idx] = buff.size() - built_trigger_bank_len_idx - 1;
380
381 // Write EventTag
382 WriteEventTagData(buff, loop->GetJEvent().GetStatus(), l3trigger);
383
384 // Write CAEN1290TDC hits
385 WriteCAEN1290Data(buff, caen1290hits, caen1290configs, Nevents);
386
387 // Write F1TDC hits
388 WriteF1Data(buff, F1hits, F1tts, F1configs, Nevents);
389
390 // Write f250 hits
391 Writef250Data(buff, f250pis, f250tts, f250wrds, Nevents);
392
393 // Write f125 hits
394 Writef125Data(buff, f125pis, f125cdcpulses, f125fdcpulses, f125tts, f125wrds, f125configs, Nevents);
395
396 // Update global header length
397 if(!buff.empty()) buff[0] = buff.size()-1;
398}
399
400//------------------
401// WriteCAEN1290Data
402//------------------
403void DEventWriterEVIO::WriteCAEN1290Data(vector<uint32_t> &buff,
404 vector<const DCAEN1290TDCHit*> &caen1290hits,
405 vector<const DCAEN1290TDCConfig*> &caen1290configs,
406 unsigned int Nevents) const
407{
408 // Create lists of F1 hit objects indexed by rocid,slot
409 // At same time, make map of module types (32channel or 48 channel)
410 map<uint32_t, map<uint32_t, vector<const DCAEN1290TDCHit*> > > modules; // outer map index is rocid, inner map index is slot
411 map<uint32_t, set<const DCAEN1290TDCConfig*> > configs;
412 for(uint32_t i=0; i<caen1290hits.size(); i++){
413 const DCAEN1290TDCHit *hit = caen1290hits[i];
414 modules[hit->rocid][hit->slot].push_back(hit);
415 }
416
417 // Copy config pointers into map indexed by rocid
418 for(uint32_t i=0; i<caen1290configs.size(); i++){
419 const DCAEN1290TDCConfig *config = caen1290configs[i];
420 configs[config->rocid].insert(config);
421 }
422
423 // Loop over rocids
424 map<uint32_t, map<uint32_t, vector<const DCAEN1290TDCHit*> > >::iterator it;
425 for(it=modules.begin(); it!=modules.end(); it++){
426 uint32_t rocid = it->first;
427
428 // Write Physics Event's Data Bank Header for this rocid
429 uint32_t data_bank_idx = buff.size();
430 buff.push_back(0); // Total bank length (will be overwritten later)
431 buff.push_back( (rocid<<16) + 0x1001 ); // 0x10=bank of banks, 0x01=1 event
432
433 // Write Config Bank
434 set<const DCAEN1290TDCConfig*> &confs = configs[rocid];
435 if(!confs.empty()){
436
437 uint32_t config_bank_idx = buff.size();
438 buff.push_back(0); // Total bank length (will be overwritten later)
439 buff.push_back( 0x00550101 ); // 0x55=config bank, 0x01=uint32_t bank, 0x01=1 event
440
441 set<const DCAEN1290TDCConfig*>::iterator it_conf;
442 for(it_conf=confs.begin(); it_conf!=confs.end(); it_conf++){
443 const DCAEN1290TDCConfig *conf = *it_conf;
444
445 uint32_t header_idx = buff.size();
446 buff.push_back(0); // Nvals and slot mask (will be filled below)
447 uint32_t Nvals = 0; // keep count of how many params we write
448 if(conf->WINWIDTH != 0xFFFF) {buff.push_back( (kPARAMCAEN1290_WINWIDTH <<16) + conf->WINWIDTH ); Nvals++;}
449 if(conf->WINOFFSET != 0xFFFF) {buff.push_back( (kPARAMCAEN1290_WINOFFSET <<16) + conf->WINOFFSET ); Nvals++;}
450
451 buff[header_idx] = (Nvals<<24) + conf->slot_mask;
452 }
453
454 // Update Config Bank length
455 buff[config_bank_idx] = buff.size() - config_bank_idx - 1;
456 }
457
458 // Write Data Block Bank Header
459 uint32_t data_block_bank_idx = buff.size();
460 buff.push_back(0); // Total bank length (will be overwritten later)
461 buff.push_back( 0x00140101 ); // 0x00=status w/ little endian, 0x14=CAEN1290TDC, 0x01=uint32_t bank, 0x01=1 event
462
463 // Loop over slots
464 map<uint32_t, vector<const DCAEN1290TDCHit*> >::iterator it2;
465 for(it2=it->second.begin(); it2!=it->second.end(); it2++){
466 uint32_t slot = it2->first;
467
468 // Write global header
469 uint32_t global_header_idx = buff.size();
470 buff.push_back( 0x40000100 + (0x01<<5) + slot ); // Global Header 0x04=global header, 0x01<<5=event count
471
472 // Write module data
473 vector<const DCAEN1290TDCHit*> &hits = it2->second;
474 uint32_t last_id = 0x0;
475 for(uint32_t i=0; i<hits.size(); i++){
476 const DCAEN1290TDCHit *hit = hits[i];
477
478 // Check if we need to write a new TDC header
479 uint32_t id = (hit->tdc_num<<24) + (hit->event_id<<12) + (hit->bunch_id);
480 if(id != last_id){
481 // Write event header
482 buff.push_back( 0x08000000 + id ); // TDC Header
483 last_id = id;
484 }
485
486 // Write Hit
487 buff.push_back( (hit->edge<<26) + (hit->channel<<21) + (hit->time&0x1fffff) );
488 }
489
490 // Write module block trailer
491 uint32_t Nwords_in_block = buff.size()-global_header_idx+1;
492 buff.push_back( 0x80000000 + (Nwords_in_block<<5) + (slot) );
493 }
494
495 // Update Data Block Bank length
496 buff[data_block_bank_idx] = buff.size() - data_block_bank_idx - 1;
497
498 // Update Physics Event's Data Bank length
499 buff[data_bank_idx] = buff.size() - data_bank_idx - 1;
500 }
501}
502
503//------------------
504// WriteF1Data
505//------------------
506void DEventWriterEVIO::WriteF1Data(vector<uint32_t> &buff,
507 vector<const DF1TDCHit*> &F1hits,
508 vector<const DF1TDCTriggerTime*> &F1tts,
509 vector<const DF1TDCConfig*> &F1configs,
510 unsigned int Nevents) const
511{
512 // Create lists of F1 hit objects indexed by rocid,slot
513 // At same time, make map of module types (32channel or 48 channel)
514 map<uint32_t, map<uint32_t, vector<const DF1TDCHit*> > > modules; // outer map index is rocid, inner map index is slot
515 map<uint32_t, map<uint32_t, MODULE_TYPE> > mod_types;
516 for(uint32_t i=0; i<F1hits.size(); i++){
517 const DF1TDCHit *hit = F1hits[i];
518 modules[hit->rocid][hit->slot].push_back(hit);
519 mod_types[hit->rocid][hit->slot] = hit->modtype;
520 }
521
522 // Copy F1 config pointers into map indexed by rocid
523 map<uint32_t, set<const DF1TDCConfig*> > configs;
524 for(uint32_t i=0; i<F1configs.size(); i++){
525 const DF1TDCConfig *config = F1configs[i];
526 configs[config->rocid].insert(config);
527 }
528
529 // Loop over rocids
530 map<uint32_t, map<uint32_t, vector<const DF1TDCHit*> > >::iterator it;
531 for(it=modules.begin(); it!=modules.end(); it++){
532 uint32_t rocid = it->first;
533
534 // Write Physics Event's Data Bank Header for this rocid
535 uint32_t data_bank_idx = buff.size();
536 buff.push_back(0); // Total bank length (will be overwritten later)
537 buff.push_back( (rocid<<16) + 0x1001 ); // 0x10=bank of banks, 0x01=1 event
538
539 // Write Config Bank
540 set<const DF1TDCConfig*> &confs = configs[rocid];
541 if(!confs.empty()){
542
543 uint32_t config_bank_idx = buff.size();
544 buff.push_back(0); // Total bank length (will be overwritten later)
545 buff.push_back( 0x00550101 ); // 0x55=config bank, 0x01=uint32_t bank, 0x01=1 event
546
547 set<const DF1TDCConfig*>::iterator it_conf;
548 for(it_conf=confs.begin(); it_conf!=confs.end(); it_conf++){
549 const DF1TDCConfig *conf = *it_conf;
550
551 uint32_t header_idx = buff.size();
552 buff.push_back(0); // Nvals and slot mask (will be filled below)
553 uint32_t Nvals = 0; // keep count of how many params we write
554 if(conf->REFCNT != 0xFFFF) {buff.push_back( (kPARAMF1_REFCNT <<16) + conf->REFCNT ); Nvals++;}
555 if(conf->TRIGWIN != 0xFFFF) {buff.push_back( (kPARAMF1_TRIGWIN <<16) + conf->TRIGWIN ); Nvals++;}
556 if(conf->TRIGLAT != 0xFFFF) {buff.push_back( (kPARAMF1_TRIGLAT <<16) + conf->TRIGLAT ); Nvals++;}
557 if(conf->HSDIV != 0xFFFF) {buff.push_back( (kPARAMF1_HSDIV <<16) + conf->HSDIV ); Nvals++;}
558 if(conf->BINSIZE != 0xFFFF) {buff.push_back( (kPARAMF1_BINSIZE <<16) + conf->BINSIZE ); Nvals++;}
559 if(conf->REFCLKDIV != 0xFFFF) {buff.push_back( (kPARAMF1_REFCLKDIV <<16) + conf->REFCLKDIV ); Nvals++;}
560
561 buff[header_idx] = (Nvals<<24) + conf->slot_mask;
562 }
563
564 // Update Config Bank length
565 buff[config_bank_idx] = buff.size() - config_bank_idx - 1;
566 }
567
568 // Write Data Block Bank Header
569 // In principle, we could write one of these for each module, but
570 // we write all modules into the same data block bank to save space.
571 // n.b. the documentation mentions Single Event Mode (SEM) and that
572 // the values in the header and even the first couple of words depend
573 // on whether it is in that mode. It appears this mode is an alternative
574 // to having a Built Trigger Bank. Our data all seems to have been taken
575 // *not* in SEM. Empirically, it looks like the data also doesn't have
576 // the initial "Starting Event Number" though the documentation does not
577 // declare that as optional. We omit it here as well.
578 uint32_t data_block_bank_idx = buff.size();
579 buff.push_back(0); // Total bank length (will be overwritten later)
580 buff.push_back( 0x001A0101 ); // 0x00=status w/ little endian, 0x1A=F1TDC, 0x01=uint32_t bank, 0x01=1 event
581
582 // Loop over slots
583 map<uint32_t, vector<const DF1TDCHit*> >::iterator it2;
584 for(it2=it->second.begin(); it2!=it->second.end(); it2++){
585 uint32_t slot = it2->first;
586 MODULE_TYPE modtype = mod_types[rocid][slot];
587
588 // Find Trigger Time object
589 const DF1TDCTriggerTime *tt = NULL__null;
590 for(uint32_t i=0; i<F1tts.size(); i++){
591 if( (F1tts[i]->rocid==rocid) && (F1tts[i]->slot==slot) ){
592 tt = F1tts[i];
593 break;
594 }
595 }
596
597 // Set itrigger number and trigger time
598 uint32_t itrigger = (tt==NULL__null) ? (Nevents&0x3FFFFF):tt->DDAQAddress::itrigger;
599 uint64_t trig_time = (tt==NULL__null) ? time(NULL__null):tt->time;
600
601 // Write module block and event headers
602 uint32_t block_header_idx = buff.size();
603 buff.push_back( 0x80000101 + (modtype<<18) + (slot<<22) ); // Block Header 0x80=data defining, modtype=F1TDC, 0x01=event block number,0x01=number of events in block
604 buff.push_back( 0x90000000 + (slot<<22) + itrigger); // Event Header
605
606 // Write Trigger Time
607 buff.push_back(0x98000000 + ((trig_time>>0 )&0x00FFFFFF));
608 buff.push_back(0x00000000 + ((trig_time>>24)&0x00FFFFFF));
609
610 // Write module data
611 vector<const DF1TDCHit*> &hits = it2->second;
612 for(uint32_t i=0; i<hits.size(); i++){
613
614 // NOTE: We write out the chip header word here (data type 8)
615 // even though it contains mostly redundant information with the time
616 // measurement words written below. The primary exception is the
617 // 9bit "F1 Chip Trigger Time" value stored in the trig_time member
618 // of the DF1TDCHit object. This is not useful in the analysis other than
619 // to verify that separate chips on the module are in sync. To do this
620 // compactly, we would need to sort the list of hits by chip number as
621 // well so that we wrote one chip header for hits on that chip. That would
622 // make this more complicated and probably slower. Given
623 // that the original data contains lots of chip header words, even for
624 // chips with no hits, writing a header word per chip will still be more
625 // compact pretty much all of the time (unless there is really high occupancy
626 // in ALL F1TDC modules!)
627 // It may be worth noting that including this chip header does increase the
628 // output file size by about 3.5% for run 2931. We may want to consider
629 // only writing it when COMPACT=0 at some point since, as noted, it is not
630 // used anywhere in the reconstruction.
631 uint32_t data_word = hits[i]->data_word;
632 uint32_t chip_header = 0xC0000000;
633 chip_header += (data_word&0x07000000); // Resolution status, overflow statuses
634 chip_header += (hits[i]->trig_time<<7)&0x01FF; // 9bit trigger time
635 chip_header += (data_word>>16)&0x3F; // chip number and channel on chip
636 buff.push_back( chip_header );
637
638 // Write Hit
639 buff.push_back( data_word ); // original data word for F1 is conveniently recorded!
640 }
641
642 // Write module block trailer
643 uint32_t Nwords_in_block = buff.size()-block_header_idx+1;
644 buff.push_back( 0x88000000 + (slot<<22) + Nwords_in_block );
645 }
646
647 // Update Data Block Bank length
648 buff[data_block_bank_idx] = buff.size() - data_block_bank_idx - 1;
649
650 // Update Physics Event's Data Bank length
651 buff[data_bank_idx] = buff.size() - data_bank_idx - 1;
652 }
653}
654
655//------------------
656// Writef250Data
657//------------------
658void DEventWriterEVIO::Writef250Data(vector<uint32_t> &buff,
659 vector<const Df250PulseIntegral*> &f250pis,
660 vector<const Df250TriggerTime*> &f250tts,
661 vector<const Df250WindowRawData*> &f250wrds,
662 unsigned int Nevents) const
663{
664 // Create lists of Pulse Integral objects indexed by rocid,slot
665 // At same time, make list of config objects to write
666 map<uint32_t, map<uint32_t, vector<const Df250PulseIntegral*> > > modules; // outer map index is rocid, inner map index is slot
667 map<uint32_t, set<const Df250Config*> > configs;
668 for(uint32_t i=0; i<f250pis.size(); i++){
669 const Df250PulseIntegral *pi = f250pis[i];
670 modules[pi->rocid][pi->slot].push_back(pi);
671
672 const Df250Config *config = NULL__null;
673 pi->GetSingle(config);
674 if(config) configs[pi->rocid].insert(config);
675 }
676
677 // Make sure entries exist for all Df250WindowRawData objects as well
678 // so when we loop over rocid,slot below we can write those out under
679 // the appropriate block header.
680 for(uint32_t i=0; i<f250wrds.size(); i++) modules[f250wrds[i]->rocid][f250wrds[i]->slot];
681
682 // Loop over rocids
683 map<uint32_t, map<uint32_t, vector<const Df250PulseIntegral*> > >::iterator it;
684 for(it=modules.begin(); it!=modules.end(); it++){
685 uint32_t rocid = it->first;
686
687 // Write Physics Event's Data Bank Header for this rocid
688 uint32_t data_bank_idx = buff.size();
689 buff.push_back(0); // Total bank length (will be overwritten later)
690 buff.push_back( (rocid<<16) + 0x1001 ); // 0x10=bank of banks, 0x01=1 event
691
692 // Write Config Bank
693 set<const Df250Config*> &confs = configs[rocid];
694 if(!confs.empty()){
695
696 uint32_t config_bank_idx = buff.size();
697 buff.push_back(0); // Total bank length (will be overwritten later)
698 buff.push_back( 0x00550101 ); // 0x55=config bank, 0x01=uint32_t bank, 0x01=1 event
699
700 set<const Df250Config*>::iterator it_conf;
701 for(it_conf=confs.begin(); it_conf!=confs.end(); it_conf++){
702 const Df250Config *conf = *it_conf;
703
704 uint32_t header_idx = buff.size();
705 buff.push_back(0); // Nvals and slot mask (will be filled below)
706 uint32_t Nvals = 0; // keep count of how many params we write
707 if(conf->NSA != 0xFFFF) {buff.push_back( (kPARAM250_NSA <<16) + conf->NSA ); Nvals++;}
708 if(conf->NSB != 0xFFFF) {buff.push_back( (kPARAM250_NSB <<16) + conf->NSB ); Nvals++;}
709 if(conf->NSA_NSB != 0xFFFF) {buff.push_back( (kPARAM250_NSA_NSB<<16) + conf->NSA_NSB); Nvals++;}
710 if(conf->NPED != 0xFFFF) {buff.push_back( (kPARAM250_NPED <<16) + conf->NPED ); Nvals++;}
711
712 buff[header_idx] = (Nvals<<24) + conf->slot_mask;
713 }
714
715 // Update Config Bank length
716 buff[config_bank_idx] = buff.size() - config_bank_idx - 1;
717 }
718
719 // Write Data Block Bank Header
720 // In principle, we could write one of these for each module, but
721 // we write all modules into the same data block bank to save space.
722 // n.b. the documentation mentions Single Event Mode (SEM) and that
723 // the values in the header and even the first couple of words depend
724 // on whether it is in that mode. It appears this mode is an alternative
725 // to having a Built Trigger Bank. Our data all seems to have been taken
726 // *not* in SEM. Empirically, it looks like the data also doesn't have
727 // the initial "Starting Event Number" though the documentation does not
728 // declare that as optional. We omit it here as well.
729 uint32_t data_block_bank_idx = buff.size();
730 buff.push_back(0); // Total bank length (will be overwritten later)
731 buff.push_back(0x00060101); // 0x00=status w/ little endian, 0x06=f250, 0x01=uint32_t bank, 0x01=1 event
732
733 // Loop over slots
734 map<uint32_t, vector<const Df250PulseIntegral*> >::iterator it2;
735 for(it2=it->second.begin(); it2!=it->second.end(); it2++){
736 uint32_t slot = it2->first;
737
738 // Find Trigger Time object
739 const Df250TriggerTime *tt = NULL__null;
740 for(uint32_t i=0; i<f250tts.size(); i++){
741 if( (f250tts[i]->rocid==rocid) && (f250tts[i]->slot==slot) ){
742 tt = f250tts[i];
743 break;
744 }
745 }
746
747 // Should we print a warning if no Trigger Time object found?
748
749 // Set itrigger number and trigger time
750 uint32_t itrigger = (tt==NULL__null) ? (Nevents&0x3FFFFF):tt->itrigger;
751 uint64_t trig_time = (tt==NULL__null) ? time(NULL__null):tt->time;
752
753 // Write module block and event headers
754 uint32_t block_header_idx = buff.size();
755 buff.push_back( 0x80040101 + (slot<<22) ); // Block Header 0x80=data defining, 0x04=FADC250, 0x01=event block number,0x01=number of events in block
756 buff.push_back( 0x90000000 + (slot<<22) + itrigger); // Event Header
757
758 // Write Trigger Time
759 buff.push_back(0x98000000 + ((trig_time>>0 )&0x00FFFFFF));
760 buff.push_back(0x00000000 + ((trig_time>>24)&0x00FFFFFF));
761
762 // Write module data
763 vector<const Df250PulseIntegral*> &pis = it2->second;
764 for(uint32_t i=0; i<pis.size(); i++){
765 const Df250PulseIntegral *pi = pis[i];
766 const Df250PulseTime *pt = NULL__null;
767 const Df250PulsePedestal *pp = NULL__null;
768 pi->GetSingle(pt);
769 pi->GetSingle(pp);
770
771 // Pulse Integral
772 if(pi->emulated == PREFER_EMULATED){
773 buff.push_back(0xB8000000 + (pi->channel<<23) + (pi->pulse_number<<21) + (pi->quality_factor<<19) + (pi->integral&0x7FFFF) );
774 }
775
776 // Pulse Time
777 if(pt && (pt->emulated == PREFER_EMULATED) ){
778 buff.push_back(0xC0000000 + (pt->channel<<23) + (pt->pulse_number<<21) + (pt->quality_factor<<19) + (pt->time&0x7FFFF) );
779 }
780
781 // Pulse Pedestal
782 if(pp && (pp->emulated == PREFER_EMULATED) ){
783 buff.push_back(0xD0000000 + (pp->channel<<23) + (pp->pulse_number<<21) + (pp->pedestal<<12) + (pp->pulse_peak&0x0FFF) );
784 }
785 }
786
787 // Write Window Raw Data
788 // This is not the most efficient, but is needed to get these under
789 // the correct block header.
790 if(!PREFER_EMULATED){
791 for(uint32_t i=0; i<f250wrds.size(); i++){
792 const Df250WindowRawData *wrd = f250wrds[i];
793 if(wrd->rocid!=rocid || wrd->slot!=slot) continue;
794
795 // IMPORTANT: At this time, the individual "not valid" bits for
796 // the samples is not preserved in the Df250WindowRawData class.
797 // We set them here only to indicate if the last sample is not
798 // valid due to there being an odd number of samples.
799 buff.push_back(0xA0000000 + (wrd->channel<<23) + (wrd->samples.size()) );
800 for(uint32_t j=0; j<(wrd->samples.size()+1)/2; j++){
801 uint32_t idx1 = 2*j;
802 uint32_t idx2 = idx1 + 1;
803 uint32_t sample_1 = wrd->samples[idx1];
804 uint32_t sample_2 = idx2<wrd->samples.size() ? wrd->samples[idx2]:0;
805 uint32_t invalid1 = 0;
806 uint32_t invalid2 = idx2>=wrd->samples.size();
807 buff.push_back( (invalid1<<29) + (sample_1<<16) + (invalid2<<13) + (sample_2<<0) );
808 }
809 }
810 }
811
812 // Write module block trailer
813 uint32_t Nwords_in_block = buff.size()-block_header_idx+1;
814 buff.push_back( 0x88000000 + (slot<<22) + Nwords_in_block );
815 }
816
817 // Update Data Block Bank length
818 buff[data_block_bank_idx] = buff.size() - data_block_bank_idx - 1;
819
820 // Update Physics Event's Data Bank length
821 buff[data_bank_idx] = buff.size() - data_bank_idx - 1;
822 }
823}
824
825//------------------
826// Writef125Data
827//------------------
828void DEventWriterEVIO::Writef125Data(vector<uint32_t> &buff,
829 vector<const Df125PulseIntegral*> &f125pis,
830 vector<const Df125CDCPulse*> &f125cdcpulses,
831 vector<const Df125FDCPulse*> &f125fdcpulses,
832 vector<const Df125TriggerTime*> &f125tts,
833 vector<const Df125WindowRawData*> &f125wrds,
834 vector<const Df125Config*> &f125configs,
835 unsigned int Nevents) const
836{
837 // Make map of rocid,slot values that have some hit data.
838 // Simultaneously make map for each flavor of hit indexed by rocid,slot
839 map<uint32_t, set<uint32_t> > modules; // outer map index is rocid, inner map index is slot
840 map<uint32_t, map<uint32_t, vector<const Df125PulseIntegral*> > > pi_hits; // outer map index is rocid, inner map index is slot
841 map<uint32_t, map<uint32_t, vector<const Df125CDCPulse* > > > cdc_hits; // outer map index is rocid, inner map index is slot
842 map<uint32_t, map<uint32_t, vector<const Df125FDCPulse* > > > fdc_hits; // outer map index is rocid, inner map index is slot
843 map<uint32_t, map<uint32_t, vector<const Df125WindowRawData*> > > wrd_hits; // outer map index is rocid, inner map index is slot
844 for(uint32_t i=0; i<f125pis.size(); i++){
845 const Df125PulseIntegral *hit = f125pis[i];
846 modules[hit->rocid].insert(hit->slot);
847 pi_hits[hit->rocid][hit->slot].push_back( hit );
848 }
849 for(uint32_t i=0; i<f125cdcpulses.size(); i++){
850 const Df125CDCPulse *hit = f125cdcpulses[i];
851 modules[hit->rocid].insert(hit->slot);
852 cdc_hits[hit->rocid][hit->slot].push_back( hit );
853 }
854 for(uint32_t i=0; i<f125fdcpulses.size(); i++){
855 const Df125FDCPulse *hit = f125fdcpulses[i];
856 modules[hit->rocid].insert(hit->slot);
857 fdc_hits[hit->rocid][hit->slot].push_back( hit );
858 }
859 for(uint32_t i=0; i<f125wrds.size(); i++){
860 const Df125WindowRawData *hit = f125wrds[i];
861 modules[hit->rocid].insert(hit->slot);
862 wrd_hits[hit->rocid][hit->slot].push_back( hit );
863 }
864
865 // Copy f125 config pointers into map indexed by just rocid
866 map<uint32_t, set<const Df125Config*> > configs;
867 for(uint32_t i=0; i<f125configs.size(); i++){
868 const Df125Config *config = f125configs[i];
869 configs[config->rocid].insert(config);
870 }
871
872 // Loop over rocids
873 map<uint32_t, set<uint32_t> >::iterator it;
874 for(it=modules.begin(); it!=modules.end(); it++){
875 uint32_t rocid = it->first;
876
877 // Write Physics Event's Data Bank Header for this rocid
878 uint32_t data_bank_idx = buff.size();
879 buff.push_back(0); // Total bank length (will be overwritten later)
880 buff.push_back( (rocid<<16) + 0x1001 ); // 0x10=bank of banks, 0x01=1 event
881
882 // Write Config Bank
883 set<const Df125Config*> &confs = configs[rocid];
884 if(!confs.empty()){
885
886 uint32_t config_bank_idx = buff.size();
887 buff.push_back(0); // Total bank length (will be overwritten later)
888 buff.push_back( 0x00550101 ); // 0x55=config bank, 0x01=uint32_t bank, 0x01=1 event
889
890 set<const Df125Config*>::iterator it_conf;
891 for(it_conf=confs.begin(); it_conf!=confs.end(); it_conf++){
892 const Df125Config *conf = *it_conf;
893
894 uint32_t header_idx = buff.size();
895 buff.push_back(0); // Nvals and slot mask (will be filled below)
896 uint32_t Nvals = 0; // keep count of how many params we write
897 if(conf->NSA != 0xFFFF) {buff.push_back( (kPARAM125_NSA <<16) + conf->NSA ); Nvals++;}
898 if(conf->NSB != 0xFFFF) {buff.push_back( (kPARAM125_NSB <<16) + conf->NSB ); Nvals++;}
899 if(conf->NSA_NSB != 0xFFFF) {buff.push_back( (kPARAM125_NSA_NSB <<16) + conf->NSA_NSB ); Nvals++;}
900 if(conf->NPED != 0xFFFF) {buff.push_back( (kPARAM125_NPED <<16) + conf->NPED ); Nvals++;}
901 if(conf->WINWIDTH!= 0xFFFF) {buff.push_back( (kPARAM125_WINWIDTH<<16) + conf->WINWIDTH); Nvals++;}
902
903 // See GlueX-doc-2274
904 if(conf->PL != 0xFFFF) {buff.push_back( (kPARAM125_PL <<16) + conf->PL ); Nvals++;}
905 if(conf->NW != 0xFFFF) {buff.push_back( (kPARAM125_NW <<16) + conf->NW ); Nvals++;}
906 if(conf->NPK != 0xFFFF) {buff.push_back( (kPARAM125_NPK <<16) + conf->NPK ); Nvals++;}
907 if(conf->P1 != 0xFFFF) {buff.push_back( (kPARAM125_P1 <<16) + conf->P1 ); Nvals++;}
908 if(conf->P2 != 0xFFFF) {buff.push_back( (kPARAM125_P2 <<16) + conf->P2 ); Nvals++;}
909 if(conf->PG != 0xFFFF) {buff.push_back( (kPARAM125_PG <<16) + conf->PG ); Nvals++;}
910 if(conf->IE != 0xFFFF) {buff.push_back( (kPARAM125_IE <<16) + conf->IE ); Nvals++;}
911 if(conf->H != 0xFFFF) {buff.push_back( (kPARAM125_H <<16) + conf->H ); Nvals++;}
912 if(conf->TH != 0xFFFF) {buff.push_back( (kPARAM125_TH <<16) + conf->TH ); Nvals++;}
913 if(conf->TL != 0xFFFF) {buff.push_back( (kPARAM125_TL <<16) + conf->TL ); Nvals++;}
914 if(conf->IBIT != 0xFFFF) {buff.push_back( (kPARAM125_IBIT <<16) + conf->IBIT ); Nvals++;}
915 if(conf->ABIT != 0xFFFF) {buff.push_back( (kPARAM125_ABIT <<16) + conf->ABIT ); Nvals++;}
916 if(conf->PBIT != 0xFFFF) {buff.push_back( (kPARAM125_PBIT <<16) + conf->PBIT ); Nvals++;}
917
918 buff[header_idx] = (Nvals<<24) + conf->slot_mask;
919 }
920
921 // Update Config Bank length
922 buff[config_bank_idx] = buff.size() - config_bank_idx - 1;
923 }
924
925 // Write Data Block Bank Header
926 // In principle, we could write one of these for each module, but
927 // we write all modules into the same data block bank to save space.
928 // n.b. the documentation mentions Single Event Mode (SEM) and that
929 // the values in the header and even the first couple of words depend
930 // on whether it is in that mode. It appears this mode is an alternative
931 // to having a Built Trigger Bank. Our data all seems to have been taken
932 // *not* in SEM. Empirically, it looks like the data also doesn't have
933 // the initial "Starting Event Number" though the documentation does not
934 // declare that as optional. We omit it here as well.
935 uint32_t data_block_bank_idx = buff.size();
936 buff.push_back(0); // Total bank length (will be overwritten later)
937 buff.push_back(0x00100101); // 0x00=status w/ little endian, 0x10=f125, 0x01=uint32_t bank, 0x01=1 event
938
939 // Loop over slots
940 set<uint32_t>::iterator it2;
941 for(it2=it->second.begin(); it2!=it->second.end(); it2++){
942 uint32_t slot = *it2;
943
944 // Find Trigger Time object
945 const Df125TriggerTime *tt = NULL__null;
946 for(uint32_t i=0; i<f125tts.size(); i++){
947 if( (f125tts[i]->rocid==rocid) && (f125tts[i]->slot==slot) ){
948 tt = f125tts[i];
949 break;
950 }
951 }
952
953 // Should we print a warning if no Trigger Time object found?
954
955 // Set itrigger number and trigger time
956 uint32_t itrigger = (tt==NULL__null) ? (Nevents&0x3FFFFF):tt->DDAQAddress::itrigger;
957 uint64_t trig_time = (tt==NULL__null) ? time(NULL__null):tt->time;
958
959 // Write module block and event headers
960 uint32_t block_header_idx = buff.size();
961 buff.push_back( 0x80080101 + (slot<<22) ); // Block Header 0x80=data defining, 0x08=FADC125, 0x01=event block number,0x01=number of events in block
962 buff.push_back( 0x90000000 + itrigger); // Event Header
963
964 // Write Trigger Time
965 buff.push_back(0x98000000 + ((trig_time>>0 )&0x00FFFFFF));
966 buff.push_back(0x00000000 + ((trig_time>>24)&0x00FFFFFF));
967
968 // Write Pulse Integral (+Pedestal and Time) data
969 vector<const Df125PulseIntegral*> &pis = pi_hits[rocid][slot];
970 for(uint32_t i=0; i<pis.size(); i++){
971 const Df125PulseIntegral *pi = pis[i];
972 const Df125PulseTime *pt = NULL__null;
973 const Df125PulsePedestal *pp = NULL__null;
974 pi->GetSingle(pt);
975 pi->GetSingle(pp);
976
977 // Pulse Integral
978 if(pi->emulated == PREFER_EMULATED){
979 buff.push_back(0xB8000000 + (pi->channel<<20) + (pi->integral&0x7FFFF) );
980 }
981
982 // Pulse Time
983 if(pt && (pt->emulated == PREFER_EMULATED) ){
984 buff.push_back(0xC0000000 + (pt->channel<<20) + (pt->pulse_number<<18) + (pt->time&0x7FFFF) );
985 }
986
987 // Pulse Pedestal
988 if(pp && (pp->emulated == PREFER_EMULATED) ){
989 buff.push_back(0xD0000000 + (pp->pulse_number<<21) + (pp->pedestal<<12) + (pp->pulse_peak&0x0FFF) );
990 }
991 }
992
993 // Write CDC Pulse data
994 vector<const Df125CDCPulse*> &cdcpulses = cdc_hits[rocid][slot];
995 for(uint32_t i=0; i<cdcpulses.size(); i++){
996 const Df125CDCPulse *pulse = cdcpulses[i];
997
998 if(pulse->emulated == PREFER_EMULATED){
999 buff.push_back( pulse->word1 );
1000 buff.push_back( pulse->word2 );
1001 }
1002 }
1003
1004 // Write FDC Pulse data
1005 vector<const Df125FDCPulse*> &fdcpulses = fdc_hits[rocid][slot];
1006 for(uint32_t i=0; i<fdcpulses.size(); i++){
1007 const Df125FDCPulse *pulse = fdcpulses[i];
1008
1009 if(pulse->emulated == PREFER_EMULATED){
1010 buff.push_back( pulse->word1 );
1011 buff.push_back( pulse->word2 );
1012 }
1013 }
1014
1015 // Write Window Raw Data
1016 // This is not the most efficient, but is needed to get these under
1017 // the correct block header.
1018 if(!PREFER_EMULATED){
1019 vector<const Df125WindowRawData*> &wrds = wrd_hits[rocid][slot];
1020 for(uint32_t i=0; i<wrds.size(); i++){
1021 const Df125WindowRawData *wrd = wrds[i];
1022
1023 // IMPORTANT: At this time, the individual "not valid" bits for
1024 // the samples is not preserved in the Df125WindowRawData class.
1025 // We set them here only to indicate if the last sample is not
1026 // valid due to there being an odd number of samples.
1027 buff.push_back(0xA0000000 + (wrd->channel<<20) + (wrd->channel<<15) + (wrd->samples.size()) );
1028 for(uint32_t j=0; j<(wrd->samples.size()+1)/2; j++){
1029 uint32_t idx1 = 2*j;
1030 uint32_t idx2 = idx1 + 1;
1031 uint32_t sample_1 = wrd->samples[idx1];
1032 uint32_t sample_2 = idx2<wrd->samples.size() ? wrd->samples[idx2]:0;
1033 uint32_t invalid1 = 0;
1034 uint32_t invalid2 = idx2>=wrd->samples.size();
1035 buff.push_back( (invalid1<<29) + (sample_1<<16) + (invalid2<<13) + (sample_2<<0) );
1036 }
1037 }
1038 }
1039
1040 // Write module block trailer
1041 uint32_t Nwords_in_block = buff.size()-block_header_idx+1;
1042 buff.push_back( 0x88000000 + (slot<<22) + Nwords_in_block );
1043 }
1044
1045 // Update Data Block Bank length
1046 buff[data_block_bank_idx] = buff.size() - data_block_bank_idx - 1;
1047
1048 // Update Physics Event's Data Bank length
1049 buff[data_bank_idx] = buff.size() - data_bank_idx - 1;
1050 }
1051}
1052
1053//------------------
1054// WriteEPICSData
1055//------------------
1056void DEventWriterEVIO::WriteEPICSData(vector<uint32_t> &buff,
1057 vector<const DEPICSvalue*> epicsValues) const
1058{
1059 // Store the EPICS event in EVIO as a bank of SEGMENTs
1060 // The first segment is a 32-bit unsigned int for the current
1061 // time. This is followed by additional SEGMENTs that are
1062 // 8-bit unsigned integer types, one for each variable being
1063 // written. All variables are written as strings in the form:
1064 //
1065 // varname=value
1066 //
1067 // where "varname" is the EPICS variable name and "value" its
1068 // value in string form. If there are multiple elements for
1069 // the PV, then value will be a comma separated list. The
1070 // contents of "value" are set in GetEPICSvalue() while
1071 // the "varname=value" string is formed here.
1072
1073 // If no values to write then return now
1074 if(epicsValues.size() == 0) return;
1075
1076 // Outermost EVIO header is a bank of segments.
1077 uint32_t epics_bank_idx = buff.size();
1078 buff.push_back(0); // Total bank length (will be overwritten later)
1079 buff.push_back( (0x60<<16) + (0xD<<8) + (0x1<<0) );
1080
1081 // Time word (unsigned 32bit SEGMENT)
1082 buff.push_back( (0x61<<24) + (0x1<<16) + (1<<0) );
1083 buff.push_back( (uint32_t)epicsValues[0]->timestamp );
1084
1085 // Loop over PVs, writing each as a SEGMENT to the buffer
1086 for(uint32_t i=0; i<epicsValues.size(); i++){
1087 const DEPICSvalue *epicsval = epicsValues[i];
1088 const string &str = epicsval->nameval;
1089 uint32_t Nbytes = str.size()+1; // +1 is for terminating 0
1090 uint32_t Nwords = (Nbytes+3)/4; // bytes needed for padding
1091 uint32_t Npad = (Nwords*4) - Nbytes;
1092
1093 buff.push_back( (0x62<<24) + (Npad<<22) + (0x7<<16) + (Nwords<<0) ); // 8bit unsigned char segment
1094
1095 // Increase buffer enough to hold this string
1096 uint32_t buff_str_idx = buff.size();
1097 buff.resize( buff_str_idx + Nwords );
1098
1099 unsigned char *ichar = (unsigned char*)&buff[buff_str_idx];
1100 for(unsigned int j=0; j<Nbytes; j++) ichar[j] = str[j]; // copy entire string including terminating 0
1101 }
1102
1103 // Update EPICS Bank length
1104 buff[epics_bank_idx] = buff.size() - epics_bank_idx - 1;
1105}
1106
1107//------------------
1108// WriteEventTagData
1109//------------------
1110void DEventWriterEVIO::WriteEventTagData(vector<uint32_t> &buff,
1111 uint64_t event_status,
1112 const DL3Trigger* l3trigger) const
1113{
1114 // Here we purposefully write the DEventTag data into a bank
1115 // based only on data extracted from other data objects, but
1116 // NOT the DEventTag object. This is so whenever an event is
1117 // written, it is guaranteed to have event tag data based on
1118 // current information as opposed to data passed in from a
1119 // previously run algorithm.
1120 uint32_t eventtag_bank_idx = buff.size();
1121
1122 uint64_t L3_status = 0;
1123 uint32_t L3_decision = 0;
1124 uint32_t L3_algorithm = 0;
1125 if(l3trigger){
1126 L3_status = l3trigger->status;
1127 L3_decision = l3trigger->L3_decision;
1128 L3_algorithm = l3trigger->algorithm;
1129 }
1130
1131 // Set L3 pass/fail status in event_status word to be written
1132 // (this is redundant with the L3_decision word written below
1133 // but makes the bits in the status word valid and costs nothing)
1134 switch(L3_decision){
1135 case DL3Trigger::kKEEP_EVENT : event_status |= kSTATUS_L3PASS; break;
1136 case DL3Trigger::kDISCARD_EVENT: event_status |= kSTATUS_L3FAIL; break;
1137 case DL3Trigger::kNO_DECISION : break;
1138 }
1139
1140 // Length and Header words
1141 buff.push_back(0); // Total bank length (will be overwritten later)
1142 buff.push_back( 0x00560101 ); // 0x56=event tag bank, 0x01=uint32_t bank, 0x01=1 event
1143
1144 // event_status
1145 buff.push_back( (event_status>> 0)&0xFFFFFFFF ); // low order word
1146 buff.push_back( (event_status>>32)&0xFFFFFFFF ); // high order word
1147
1148 // L3_status
1149 buff.push_back( (L3_status>> 0)&0xFFFFFFFF ); // low order word
1150 buff.push_back( (L3_status>>32)&0xFFFFFFFF ); // high order word
1151
1152 // L3_decision
1153 buff.push_back( L3_decision );
1154
1155 // L3_algorithm
1156 buff.push_back( L3_algorithm );
1157
1158 // Update event tag Bank length
1159 buff[eventtag_bank_idx] = buff.size() - eventtag_bank_idx - 1;
1160}
1161
1162
1163//------------------
1164// WriteBORData
1165//------------------
1166void DEventWriterEVIO::WriteBORData(JEventLoop *loop, vector<uint32_t> &buff) const
1167{
1168 // The Begin-Of-Run (BOR) record is a special record that should show up
1169 // at the beginning of each EVIO file and any time a new run starts during a file
1170 // We want to preserve its format, so the easiest way to handle it is just to copy
1171 // it straight to the output. It's always (so far) saved as a single event,
1172 // consisting of a bank of banks of config information
1173
1174 // grab buffer corresponding to this event
1175 // note that we get everything after the EVIO block header
1176 void *ref = loop->GetJEvent().GetRef();
1177 uint32_t *in_buff = JEventSource_EVIO::GetEVIOBufferFromRef(ref);
1178 uint32_t buff_size = JEventSource_EVIO::GetEVIOBufferSizeFromRef(ref); // this is much larger than the bank size - not sure why
Value stored to 'buff_size' during its initialization is never read
1179
1180 uint32_t Nwords = in_buff[0]; // number of words in BOR config bank
1181 // copy entire bank
1182 for(uint32_t i=0; i<Nwords+1; i++) buff.push_back( in_buff[i] );
1183
1184}