Difference between revisions of "OWG Meeting 31-Mar-2010"

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* Announcements
 
* Announcements
 +
** CNU student
 
* Review of minutes from [[OWG Meeting 17-Mar-2010 | 17-Mar-2010]] meeting
 
* Review of minutes from [[OWG Meeting 17-Mar-2010 | 17-Mar-2010]] meeting
 +
* Emerson visit - Dave A, Elliott
 +
* cMsg and SSH tunnels - Carl T, David L, Elliott
 +
* JANA/CLARA - Dave L
 +
* DANAEVIO and EVIO improvements - Elliott
 
* Trigger test stand - Alex S
 
* Trigger test stand - Alex S
−
* cMsg and SSH tunnels - David L, Carl T, Elliott W
+
* Coil test update - Elliott, Yi
−
* DANAEVIO and EVIO improvements - Elliott W
+
* Other electronics and trigger status reports - Fernando, Chris, Ben, Ed, Alex, Dave, William, Bryan
−
* Coil test update - Elliott W
+
−
* Other electronics and trigger status reports - Fernando, Chris, Ben, Ed, Alex, Dave, William
+
  
  
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=Minutes=
 
=Minutes=
 +
 +
Attendees:  Elliott W, Simon T, Beni Z, Dave A, Carl T, William G, Dave L, Bryan M, Yi Q, Alex S.
 +
 +
 +
'''Emerson Technical Sales personnel visit'''
 +
 +
* Emerson purchased the division of Motorolla that supplied VME single board processors.
 +
* They continue to design new PPC boards and have just introduced an Intel-based board (Core i7).
 +
* All boards run Linux and VxWorks. The Intel-based boards can run Windows (sorry, Beni...).
 +
* Dave Abbott wants to move everyone to Intel-based boards, although VxWorks will be around for a while.
 +
* Dave will purchase Emerson, GE-Fanuc and other boards, test them, and make recommendations to the halls.
 +
* Full order from JLab for 12 GeV will be large, perhaps as many as 150 boards (maybe more!).
 +
* Order will involve staged delivery and payment, back-end loaded as much as possible.
 +
* Hall D needs around 70 boards, maybe more for spares and test setups.
 +
* Hall D owns two GE-Fanuc boards;  one is at IU and Dave has the other (for software development).
 +
* Embedded processors use less power, but are less powerful.
 +
* Emerson expects seven year processor family lifetime from Intel.
 +
* New boards have lots of on-board memory, can boot from local memory instead of network if desired.
 +
 +
 +
'''cMsg Tunnels'''
 +
 +
* Carl reported that ssh tunnels now work with cMsg.
 +
* He had to modify the internal protocol to accommodate tunnels, so latest version is NOT backwards compatible.
 +
* Dave L will test with RootSpy.
 +
 +
 +
'''JANA/CLARA'''
 +
 +
* JANA is the Hall D reconstruction/analysis framework (author Dave Lawrence).
 +
* CLARA is the Hall B service-oriented architecture framework (author Vardan Gyurjyan).
 +
* Hall B is considering using JANA, and Hall D is considering using CLARA.
 +
* Possible CLARA applications for Hall D are in the online monitoring farm and to distribute calibration constants, the B field, etc.
 +
* Dave and Elliott will investigate how well CLARA can work with JANA.
 +
 +
 +
'''DANAEVIO'''
 +
 +
* Elliott is almost done with serializing DANA objects into an EVIO file (everything is checked in).
 +
* Currently 19 DANA objects are converted, including object id's and associated objects.
 +
* Elliott will add additional DANA objects as needed (not difficult).
 +
* Default EVIO tag/num dictionary provided, user can override if desired.
 +
* Last thing to do on DANA->EVIO is addition of bank of strings, currently not supported in EVIO.  Elliott will add this to EVIO and finish DANAEVIO in the next week or so.
 +
* Next big step is to read EVIO file and fill DANA objects.  Dave L will work on this with help from Elliott.
 +
 +
 +
'''Trigger Test Stand'''
 +
 +
* Alex reported on the latest progress in the trigger test stand.
 +
* Hai is almost done programming the FPGA to allow loading of test pulse height data to test trigger algorithms ("flash replay mode").
 +
* Dave A will provide libraries to allow access to the new FPGA features.
 +
* One constraint is that all 16 channels use the same fake data.
 +
 +
 +
 +
'''Coil Test'''
 +
 +
* Controls racks constructed, wiring has begun.
 +
* We will get technical help from Accelerator groups now that the accelerator is running.
 +
* Coil 2 is being opened up.
 +
* Coil 1 is being closed.
 +
* IUCF wants 6 months to complete coil 3 LN2 shield replacement.
 +
* When coil 1 can be moved we will begin construction of the test apparatus.
 +
* EWEB module appears to be working, Elliott created some test web pages that display real PLC data.
 +
* Yi is just getting started with the HMI software.  He hopes to borrow screens from Hall C.
 +
* Preparations have begun for OSP and COO reviews.  Authors and subject matter experts have been (tentatively) identified.
 +
 +
 +
'''DAQ'''
 +
 +
* Bryan reported that they now get 80 MB/s network data throughtput.
 +
* Across the VME backplane they get 200 MB/s from the FADC using two-edge source-synchronous transfers.

Latest revision as of 12:29, 2 April 2010

Agenda

  • Announcements
    • CNU student
  • Review of minutes from 17-Mar-2010 meeting
  • Emerson visit - Dave A, Elliott
  • cMsg and SSH tunnels - Carl T, David L, Elliott
  • JANA/CLARA - Dave L
  • DANAEVIO and EVIO improvements - Elliott
  • Trigger test stand - Alex S
  • Coil test update - Elliott, Yi
  • Other electronics and trigger status reports - Fernando, Chris, Ben, Ed, Alex, Dave, William, Bryan


Time/Location

1:30 PM Wed 31-Mar-2010 CC F326


Announcements

Next Meeting

Tentative: 1:30 PM Wed 14-Apr-2010


New Action Items from this Meeting

Minutes

Attendees: Elliott W, Simon T, Beni Z, Dave A, Carl T, William G, Dave L, Bryan M, Yi Q, Alex S.


Emerson Technical Sales personnel visit

  • Emerson purchased the division of Motorolla that supplied VME single board processors.
  • They continue to design new PPC boards and have just introduced an Intel-based board (Core i7).
  • All boards run Linux and VxWorks. The Intel-based boards can run Windows (sorry, Beni...).
  • Dave Abbott wants to move everyone to Intel-based boards, although VxWorks will be around for a while.
  • Dave will purchase Emerson, GE-Fanuc and other boards, test them, and make recommendations to the halls.
  • Full order from JLab for 12 GeV will be large, perhaps as many as 150 boards (maybe more!).
  • Order will involve staged delivery and payment, back-end loaded as much as possible.
  • Hall D needs around 70 boards, maybe more for spares and test setups.
  • Hall D owns two GE-Fanuc boards; one is at IU and Dave has the other (for software development).
  • Embedded processors use less power, but are less powerful.
  • Emerson expects seven year processor family lifetime from Intel.
  • New boards have lots of on-board memory, can boot from local memory instead of network if desired.


cMsg Tunnels

  • Carl reported that ssh tunnels now work with cMsg.
  • He had to modify the internal protocol to accommodate tunnels, so latest version is NOT backwards compatible.
  • Dave L will test with RootSpy.


JANA/CLARA

  • JANA is the Hall D reconstruction/analysis framework (author Dave Lawrence).
  • CLARA is the Hall B service-oriented architecture framework (author Vardan Gyurjyan).
  • Hall B is considering using JANA, and Hall D is considering using CLARA.
  • Possible CLARA applications for Hall D are in the online monitoring farm and to distribute calibration constants, the B field, etc.
  • Dave and Elliott will investigate how well CLARA can work with JANA.


DANAEVIO

  • Elliott is almost done with serializing DANA objects into an EVIO file (everything is checked in).
  • Currently 19 DANA objects are converted, including object id's and associated objects.
  • Elliott will add additional DANA objects as needed (not difficult).
  • Default EVIO tag/num dictionary provided, user can override if desired.
  • Last thing to do on DANA->EVIO is addition of bank of strings, currently not supported in EVIO. Elliott will add this to EVIO and finish DANAEVIO in the next week or so.
  • Next big step is to read EVIO file and fill DANA objects. Dave L will work on this with help from Elliott.


Trigger Test Stand

  • Alex reported on the latest progress in the trigger test stand.
  • Hai is almost done programming the FPGA to allow loading of test pulse height data to test trigger algorithms ("flash replay mode").
  • Dave A will provide libraries to allow access to the new FPGA features.
  • One constraint is that all 16 channels use the same fake data.


Coil Test

  • Controls racks constructed, wiring has begun.
  • We will get technical help from Accelerator groups now that the accelerator is running.
  • Coil 2 is being opened up.
  • Coil 1 is being closed.
  • IUCF wants 6 months to complete coil 3 LN2 shield replacement.
  • When coil 1 can be moved we will begin construction of the test apparatus.
  • EWEB module appears to be working, Elliott created some test web pages that display real PLC data.
  • Yi is just getting started with the HMI software. He hopes to borrow screens from Hall C.
  • Preparations have begun for OSP and COO reviews. Authors and subject matter experts have been (tentatively) identified.


DAQ

  • Bryan reported that they now get 80 MB/s network data throughtput.
  • Across the VME backplane they get 200 MB/s from the FADC using two-edge source-synchronous transfers.
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