Difference between revisions of "Configuration for 2025 run"
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| − | All signal cables are connected to the | + | All signal cables are connected to the Flash ADC in Slot 3 of the D2-4-BOT CCAL crate. |
| − | The TAC is connected to the former CCAL crate. The reconstruction of TAC hits (and EPICS scalers) | + | The TAC is connected to the former CCAL crate. The reconstruction of TAC hits (and EPICS scalers) |
| − | the CCAL translation table. | + | is performed using the CCAL translation table. |
| − | + | ||
| + | The TAC high voltage (HV) is supplied by the CAEN module in Slot 10 of the halldcaenhv10 crate | ||
| + | (D2-8-MID, IP: 129.57.26.211). This crate also contains HV modules for the DIRC. | ||
| + | |||
| + | The mapping of TAC channels is detailed in the table below. | ||
| + | |||
{|border="1" cellpadding="5" cellspacing="0" align="center" | {|border="1" cellpadding="5" cellspacing="0" align="center" | ||
Latest revision as of 13:42, 6 March 2025
All signal cables are connected to the Flash ADC in Slot 3 of the D2-4-BOT CCAL crate. The TAC is connected to the former CCAL crate. The reconstruction of TAC hits (and EPICS scalers) is performed using the CCAL translation table.
The TAC high voltage (HV) is supplied by the CAEN module in Slot 10 of the halldcaenhv10 crate (D2-8-MID, IP: 129.57.26.211). This crate also contains HV modules for the DIRC.
The mapping of TAC channels is detailed in the table below.
| TAC channel | ADC channel | CCAL (column, row) | HV channel (Slot 10, D2-8-MID) |
|---|---|---|---|
| 1 | 0 | 1, 2 | 1 |
| 2 | 1 | 1, 3 | 2 |
| 3 | 2 | 1, 4 | 3 |
| 4 | 3 | 1, 5 | 4 |
| 5 | 4 | 2, 1 | 5 |
| 6 | 5 | 2, 2 | 6 |
| 7 | 6 | 2, 3 | 7 |
| 8 | 7 | 2, 4 | 8 |
| 9 | 8 | 2, 5 | 9 |
The definition of channels in the 3 x 3 PbWO4 array:
9 8 7
6 5 4
3 2 1
