Difference between revisions of "CDC readout requirements"
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I am using units of sample/10 because the upsampling works in units of sample/5 and it is straightforward to find the threshold crossing and then interpolate using units of sample/10. Multiplying this x 1.25 to give ns is possible but it makes the output number larger without adding precision, and it uses more clock cycles (ie the calculation takes longer), I think it is better to keep the firmware to the minimum and then convert to ns later on somewhere else. If the FDC needs better precision than 0.8ns then I could have it interpolate further but this takes yet more clock cycles. | I am using units of sample/10 because the upsampling works in units of sample/5 and it is straightforward to find the threshold crossing and then interpolate using units of sample/10. Multiplying this x 1.25 to give ns is possible but it makes the output number larger without adding precision, and it uses more clock cycles (ie the calculation takes longer), I think it is better to keep the firmware to the minimum and then convert to ns later on somewhere else. If the FDC needs better precision than 0.8ns then I could have it interpolate further but this takes yet more clock cycles. | ||
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+ | <h3>QF time</h3> 1 bit (firm) | ||
+ | 1 bit to indicate that less accurate time is being returned | ||
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+ | <h3>QF overflow</h3> 3 bits, 0-7 | ||
+ | Count up to 6 (and indicate 7 or more) overflow samples; this info might also be deduced from the integral if it maxes out. | ||
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<h3>Integral</h3> 16 bits, 0-65536 (OK to scale down by larger factor) | <h3>Integral</h3> 16 bits, 0-65536 (OK to scale down by larger factor) | ||
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Scale full range 0-4095 to fit into however bits are available. Scale x 1/8 to fit into 9 bits? | Scale full range 0-4095 to fit into however bits are available. Scale x 1/8 to fit into 9 bits? | ||
Could be useful for dedx; also MIP gives a handle on gain shifts | Could be useful for dedx; also MIP gives a handle on gain shifts | ||
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Revision as of 09:58, 11 March 2014
Aim to establish how many bits are needed for each quantity, then later fit the quantities into the words.
First word has (header +) 15 bits available for data Second word has 31 bits for data
Time
11 bits, 0-2047, firm (minimum)I expect max drift time of 155 samples, to record time in tenths of samples, I need max value of 1550 which requires 11 bits, 0-2047.
I am using units of sample/10 because the upsampling works in units of sample/5 and it is straightforward to find the threshold crossing and then interpolate using units of sample/10. Multiplying this x 1.25 to give ns is possible but it makes the output number larger without adding precision, and it uses more clock cycles (ie the calculation takes longer), I think it is better to keep the firmware to the minimum and then convert to ns later on somewhere else. If the FDC needs better precision than 0.8ns then I could have it interpolate further but this takes yet more clock cycles.
QF time
1 bit (firm)1 bit to indicate that less accurate time is being returned
QF overflow
3 bits, 0-7Count up to 6 (and indicate 7 or more) overflow samples; this info might also be deduced from the integral if it maxes out.
Integral
16 bits, 0-65536 (OK to scale down by larger factor)Scale integral x 1/2 to fit into 16 bits. This is enough for 130 samples at 1000, scaled x 1/2.
Pedestal
8 bits, 0-255 (OK to scale this down by factor of 4 to take up 6 bits instead).No scaling; output 255 for 255 and higher. Expect pedestal width < 20. Set pedestal height at 4sigma=80 and expect it to vary between 1sigma=20 and 7sigma=140.
Max amplitude
Scale full range 0-4095 to fit into however bits are available. Scale x 1/8 to fit into 9 bits? Could be useful for dedx; also MIP gives a handle on gain shifts