Difference between revisions of "Configuration for 2025 run"

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Line 5: Line 5:
  
 
{|border="1" cellpadding="5" cellspacing="0" align="center"
 
{|border="1" cellpadding="5" cellspacing="0" align="center"
 +
! scope="col" | TAC channel
 
! scope="col" | ADC channel
 
! scope="col" | ADC channel
 
! scope="col" | CCAL (column, row)
 
! scope="col" | CCAL (column, row)
 +
! scope="col" | HV channel
 
|-
 
|-
 +
|  1
 
|  0
 
|  0
 
|  1, 2
 
|  1, 2
 +
|  1
 
|-
 
|-
 +
|  2
 
|  1
 
|  1
 
|  1, 3
 
|  1, 3
 +
|  2
 
|-
 
|-
 +
|  3
 
|  2
 
|  2
 
|  1, 4
 
|  1, 4
 +
|  3
 
|-
 
|-
 +
|  4
 
|  3
 
|  3
 
|  1, 5
 
|  1, 5
 +
|  4
 
|-
 
|-
 +
|  5
 
|  4
 
|  4
 
|  2, 1
 
|  2, 1
 +
|  5
 
|-
 
|-
 +
|  6
 
|  5
 
|  5
 
|  2, 2
 
|  2, 2
 +
|  6
 
|-
 
|-
 +
|  7
 
|  6
 
|  6
 
|  2, 3
 
|  2, 3
 +
|  7
 
|-
 
|-
 +
|  8
 
|  7
 
|  7
 
|  2, 4
 
|  2, 4
 +
|  8
 
|-
 
|-
 +
|  9
 
|  8
 
|  8
 
|  2, 5
 
|  2, 5
 +
|  9
 
|}
 
|}
 +
 +
 +
The TAC HV is provided by the CAEN module in Slot 7 of the halldcaenhv10 (D2-8-MID) crate. This crate also contains modules for the DIRC.
 +
 +
The channel assignment is as follows:
 +
 +
TAC CH 1  - HV CH 1
 +
TAC CH 9  - HV CH 9

Revision as of 13:29, 6 March 2025

  • Connection of signal cables (D2-4-BOT, ccal crate)

All signal cables are connected to the flash ADC in Slot 3

TAC channel ADC channel CCAL (column, row) HV channel
1 0 1, 2 1
2 1 1, 3 2
3 2 1, 4 3
4 3 1, 5 4
5 4 2, 1 5
6 5 2, 2 6
7 6 2, 3 7
8 7 2, 4 8
9 8 2, 5 9


The TAC HV is provided by the CAEN module in Slot 7 of the halldcaenhv10 (D2-8-MID) crate. This crate also contains modules for the DIRC.

The channel assignment is as follows:

TAC CH 1 - HV CH 1 TAC CH 9 - HV CH 9