FADC algorithm
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Revision as of 16:02, 30 July 2013 by Zihlmann (Talk | contribs) (Created page with "A first proposal of a generic algorithm to determine the charge and pedestal (not time). Consider first that the hardware has the following feature: * The ADC has 72 channels wit...")
A first proposal of a generic algorithm to determine the charge and pedestal (not time). Consider first that the hardware has the following feature:
- The ADC has 72 channels with 12 first order FPGAs, that meas each FPGA handles 6 channels
- Because every other channel is directed to a masoning board no neighboring channels are within any given FPGA. For example channels 0,2,4,6,8,10 are in the first FPGA located on the main board, channels 1,3,5,7,9,11 are in the first FPGA on the masoning board.
