CDC run 1280 bad events

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Run 1280 Evt 14992 roc 26 slot 3 chan 56
original
upsampled
both


Below are the original sample values followed by the upsampled values for that same time, and then at 4 time-steps of 1.6ns later (calculated in C++, floating point arith). The first upsampled value should match the original value +/- 1. Clearly something is wrong here, first with the original data (contains discontinuities) and then with the upsampled data.

sample: 45  original:   57  upsampled:    57    54    50    48    46
sample: 46  original:   44  upsampled:    45    44    45    46    49
sample: 47  original:   51  upsampled:    51    55    59    63    67
sample: 48  original:   71  upsampled:    72    76    81    86    92
sample: 49  original:   94  upsampled:    98   103   107   110   110
sample: 50  original:  117  upsampled:   108   107   113   130   162
sample: 51  original:  174  upsampled:   207   260   311   346   353
sample: 52  original:  375  upsampled:   331   287   241   220   245
sample: 53  original:  257  upsampled:   334   485   680   889  1075
sample: 54  original: 1287  upsampled:  1212  1289  1316  1316  1323
sample: 55  original: 1294  upsampled:  1365  1458  1602  1780  1962
sample: 56  original: 2196  upsampled:  2126  2254  2342  2399  2436
sample: 57  original: 2423  upsampled:  2469  2502  2534  2552  2542

Used C++ version of the integer arithmetic that is used in the VHDL code

C++ leading edge algo output: Searching for ADC value >= 300, ADC values surrounding the threshold crossing are

  ADC[41] 108
  ADC[42] 98
  ADC[43] 89
  ADC[44] 77
  ADC[45] 57
  ADC[46] 44
  ADC[47] 51
  ADC[48] 71
  ADC[49] 94
  ADC[50] 117
  ADC[51] 174
  ADC[52] 375

Subset of ADC values sent to the upsampling routine:
adc_subset[0] 89
adc_subset[1] 77
adc_subset[2] 57
... 
adc_subset[9] 375
adc_subset[10] 257
adc_subset[11] 1287
... up to 
adc_subset[14] 2423

thresholds: hi 231 lo 111
threshold 231 met or exceeded by sample 9 value 375

adc[8] 174
adc[7] 117
adc[6] 94

threshold 111 met or preceded by sample 6 value 94
itime1 60 x 0.1 samples

The low timing threshold is now known to be between samples 6 and 7, so upsampled points are calculated from 5.8 to 7.2. These are searched from the last point back to the first, looking for a value which matches or is lower than the low timing threshold (111).

upsampled 0 91 upsampled 1 97 upsampled 2 102 upsampled 3 107 upsampled 4 110 upsampled 5 109 upsampled 6 107 upsampled 7 107

threshold 111 met or preceded by upsampled point 7 value 107 itime2 14 x 0.1 samples

The next stage in the calculation is to interpolate between the two points surrounding the threshold crossing but in this case the first point (upsampled 7) was less than the threshold, it all goes horribly wrong.

denom -107 limit 8

Upsampled values 1 (97) and 6 (107) should match the raw values for samples 6 (94) and 7 (117), respectively. They do not, as can be seen in the plot at the top of the page.


VHDL simulation output:

at 308 ns(1): Note:                                            upsampled: iubuf(0) 91 (/findtime_tb/uut/).
at 460 ns(1): Note:                                            upsampled: iubuf(1) 97 (/findtime_tb/uut/).
at 612 ns(1): Note:                                            upsampled: iubuf(2) 102 (/findtime_tb/uut/).
at 748 ns(1): Note:                                            upsampled: iubuf(3) 107 (/findtime_tb/uut/).
at 884 ns(1): Note:                                            upsampled: iubuf(4) 110 (/findtime_tb/uut/).
at 1036 ns(1): Note:                                            upsampled: iubuf(5) 109 (/findtime_tb/uut/).
at 1188 ns(1): Note:                                            upsampled: iubuf(6) 107 (/findtime_tb/uut/).
at 1340 ns(1): Note:                                            upsampled: iubuf(7) 107 (/findtime_tb/uut/).

at 1348 ns(1): Note: i 7 adc val 107 lo thres 111 (/findtime_tb/uut/).
at 1348 ns(1): Note: adc_sample_lo2 7 (/findtime_tb/uut/).
at 1348 ns(1): Note: itime2 14 x 0.1samples (/findtime_tb/uut/).
at 1356 ns(1): Note: denom -107 (/findtime_tb/uut/).
at 1356 ns(1): Note: limit 8 (/findtime_tb/uut/).
at 1364 ns(1): Note:  sum -107 ifrac 1 (/findtime_tb/uut/).
at 1372 ns(1): Note:  sum -214 ifrac 2 (/findtime_tb/uut/).
at 1380 ns(1): Note:  sum -321 ifrac 3 (/findtime_tb/uut/).
at 1388 ns(1): Note:  sum -428 ifrac 4 (/findtime_tb/uut/).

The good news is that the VHDL and C++ codes give the same results before VHDL descends into a spiral of doom.

The fix for the bug would be to test