Difference between revisions of "DIRC Planning for FY16"

From GlueXWiki
Jump to: navigation, search
m (Jrsteven moved page Planning for FY16 to DIRC Planning for FY16)
Line 2: Line 2:
  
 
== Support Structure ==
 
== Support Structure ==
* Milestone: Design finalized May-June 2016
+
* '''Milestone''': Design finalized May-June 2016
 
** Optical box length needed to determine how they will be supported
 
** Optical box length needed to determine how they will be supported
 
** Design review by JLab (ie. Tim et. al.): assume ~4 weeks
 
** Design review by JLab (ie. Tim et. al.): assume ~4 weeks
* Milestone: Fabrication start July-August 2016
+
* '''Milestone''': Fabrication start July-August 2016
 
** Get started on contract with IU: Statement of Work and Sole Source Justification
 
** Get started on contract with IU: Statement of Work and Sole Source Justification
  
 
== Optical Boxes ==
 
== Optical Boxes ==
* Milestone: Design finalized June-July 2016
+
* '''Milestone''': Design finalized June-July 2016
 
** Is additional support for engineering time at MIT needed?
 
** Is additional support for engineering time at MIT needed?
 
** Design review by JLab (ie. Tim et. al.): assume ~4 weeks
 
** Design review by JLab (ie. Tim et. al.): assume ~4 weeks
Line 16: Line 16:
  
 
== Electronics ==
 
== Electronics ==
* Milestone: ASIC and Adapter board order submitted July-August 2016
+
* '''Milestone''': ASIC and Adapter board order submitted July-August 2016
 
** Some delay in MAROC chip packaging, so CLAS order of ASIC and Adapter boards may be delayed.
 
** Some delay in MAROC chip packaging, so CLAS order of ASIC and Adapter boards may be delayed.
* Opportunity: Possible use of FPGA boards from CLAS
+
* '''Opportunity''': Possible use of FPGA boards from CLAS
 
** The FPGA boards for CLAS were produced with wrong hole size, but could be used for GlueX.   
 
** The FPGA boards for CLAS were produced with wrong hole size, but could be used for GlueX.   
 
** Could assemble boards ~now.  Waiting for quote from vendor to evaluate cost reduction.
 
** Could assemble boards ~now.  Waiting for quote from vendor to evaluate cost reduction.
  
 
== Transportation ==
 
== Transportation ==
* Milestone: Shipping crate design finalized October 2016
+
* '''Milestone''': Shipping crate design finalized October 2016
 
** Technically FY17, but considering additional transportation tests planed, should we start earlier?
 
** Technically FY17, but considering additional transportation tests planed, should we start earlier?

Revision as of 09:39, 15 January 2016

Support Structure

  • Milestone: Design finalized May-June 2016
    • Optical box length needed to determine how they will be supported
    • Design review by JLab (ie. Tim et. al.): assume ~4 weeks
  • Milestone: Fabrication start July-August 2016
    • Get started on contract with IU: Statement of Work and Sole Source Justification

Optical Boxes

  • Milestone: Design finalized June-July 2016
    • Is additional support for engineering time at MIT needed?
    • Design review by JLab (ie. Tim et. al.): assume ~4 weeks
  • Milestone: Fabrication start August-September 2016
    • Get started on contract with MIT: Statement of Work and Sole Source Justification

Electronics

  • Milestone: ASIC and Adapter board order submitted July-August 2016
    • Some delay in MAROC chip packaging, so CLAS order of ASIC and Adapter boards may be delayed.
  • Opportunity: Possible use of FPGA boards from CLAS
    • The FPGA boards for CLAS were produced with wrong hole size, but could be used for GlueX.
    • Could assemble boards ~now. Waiting for quote from vendor to evaluate cost reduction.

Transportation

  • Milestone: Shipping crate design finalized October 2016
    • Technically FY17, but considering additional transportation tests planed, should we start earlier?