Difference between revisions of "FA125 chip occupancy"
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<h1>Run 11437, 212nA</h1> | <h1>Run 11437, 212nA</h1> | ||
| − | From the first 1000 events in run 11437, 50 um diamond, 1200A solenoid, 212 nA beam. | + | From the first 1000 events in run 11437, 50 um diamond, PERP, 1200A solenoid, 212 nA beam. |
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Revision as of 15:36, 10 August 2016
Run 11663, 80nA
From the first 1000 events in run 11663, 50 um diamond, PARA, 1345A solenoid, 80 nA beam. Plotted number of hits in each of the chips per event, channels 0-5 are on one chip, 6-11 are on the next, etc, eg event 21 has only 1 hit on roc25 slot3, and that is for the 2nd chip, so the entry in the histogram for roc25slot3 is 1. The crates are plotted separately.
CDC total 720000 zero 678645 nonzero 41355 zero/total 94.3 % count 0 / total 94.25625000 % count 1 / total 3.78458333 % count 2 / total 1.20347222 % count 3 / total 0.52069444 % count 4 / total 0.14902778 % count 5 / total 0.05250000 % count 6 / total 0.03347222 % FDC total 1800000 zero 1704945 nonzero 95055 zero/total 94.7 % count 0 / total 94.71916667 % count 1 / total 1.14705556 % count 2 / total 1.13011111 % count 3 / total 1.11655556 % count 4 / total 1.05961111 % count 5 / total 0.52822222 % count 6 / total 0.29927778 %
Run 11437, 212nA
From the first 1000 events in run 11437, 50 um diamond, PERP, 1200A solenoid, 212 nA beam.
CDC total 720000 zero 718425 nonzero 1575 zero/total 99.8 % count 0 / total 99.78125000 % count 1 / total 0.10638889 % count 2 / total 0.07805556 % count 3 / total 0.02916667 % count 4 / total 0.00458333 % count 5 / total 0.00055556 % count 6 / total 0.00000000 % FDC total 1800000 zero 1797374 nonzero 2626 zero/total 99.9 % count 0 / total 99.85411111 % count 1 / total 0.08911111 % count 2 / total 0.02266667 % count 3 / total 0.01200000 % count 4 / total 0.00977778 % count 5 / total 0.00755556 % count 6 / total 0.00477778 %
