FA125 chip occupancy

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Run 11663, 80nA

From the first 1000 events in run 11663, 50 um diamond, PARA, 1345A solenoid, 80 nA beam. Plotted number of hits in each of the chips per event, channels 0-5 are on one chip, 6-11 are on the next, etc, eg event 21 has only 1 hit on roc25 slot3, and that is for the 2nd chip, so the entry in the histogram for roc25slot3 is 1. The crates are plotted separately.

At present the plots over-represent the zeros by 15/13 as they include zeros for the two unused slots.

CDC crates, fa125 chip occupancy in run 11663
CDC crates, fa125 chip occupancy in run 11663
FDC crates, fa125 chip occupancy in run 11663
FDC crates, fa125 chip occupancy in run 11663

[Run 11663 RCDB]

CDC total 720000 zero 678645 nonzero 41355 zero/total 94.3 % 
 count 0 / total  94.25625000 % 
 count 1 / total  3.78458333 % 
 count 2 / total  1.20347222 % 
 count 3 / total  0.52069444 % 
 count 4 / total  0.14902778 % 
 count 5 / total  0.05250000 % 
 count 6 / total  0.03347222 % 

FDC total 1800000 zero 1704945 nonzero 95055 zero/total 94.7 % 
 count 0 / total  94.71916667 % 
 count 1 / total  1.14705556 % 
 count 2 / total  1.13011111 % 
 count 3 / total  1.11655556 % 
 count 4 / total  1.05961111 % 
 count 5 / total  0.52822222 % 
 count 6 / total  0.29927778 % 

Run 11437, 212nA

From the first 1000 events in run 11437 file 001, 50 um diamond, PERP, 1200A solenoid, 212 nA beam.


(Beni was right)


CDC crates, fa125 chip occupancy in run 11437
CDC crates, fa125 chip occupancy in run 11437
FDC crates, fa125 chip occupancy in run 11437
FDC crates, fa125 chip occupancy in run 11437

[Run 11437 RCDB]

CDC total 720000 zero 678261 nonzero 41739 zero/total 94.2 % 
 count 0 / total  94.20291667 % 
 count 1 / total  3.73777778 % 
 count 2 / total  1.28583333 % 
 count 3 / total  0.55111111 % 
 count 4 / total  0.14819444 % 
 count 5 / total  0.04500000 % 
 count 6 / total  0.02916667 % 

FDC total 1800000 zero 1690179 nonzero 109821 zero/total 93.9 % 
 count 0 / total  93.89883333 % 
 count 1 / total  1.35650000 % 
 count 2 / total  1.30600000 % 
 count 3 / total  1.25233333 % 
 count 4 / total  1.20744444 % 
 count 5 / total  0.60266667 % 
 count 6 / total  0.37622222 % 


Tally of hits per FPGA chip, CDC modules
# hits # occurrences
0 582261
1 26912
2 9258
3 3968
4 1067
5 324
6 210


Chip occupancy calculation for CDC:



Total # hits possible = 6 * 624,000.

Data file contains 720,000 entries, one for each of 4 crates x 15 boards x 12 chips per board x 1000 events. Nonexistent boards in slots 11 and 12 were included in the count (these have 96,000 entries of count=0). There are 624,000 entries for real boards.

 ((1*26912)+(2*9258)+(3*3968)+(4*1067)+(5*324)+(6*210))/(6*624000.0) = 1.72e-02

so this is an average of 1.7% occupancy.