FA125 chip occupancy
The FA125 signal processing (hit search & analysis) is handled on the 12 front end FPGA chips, 6 channels each, 72 channels per module.
The plots below show the occupancy for the busiest chip, module and roc for the CDC and FDC in the high luminosity test runs.
Run 11663, 80nA
From the first 1000 events in run 11663, 50 um diamond, PARA, 1345A solenoid, 80 nA beam. Plotted number of hits in each of the chips per event, channels 0-5 are on one chip, 6-11 are on the next, etc, eg event 21 has only 1 hit on roc25 slot3, and that is for the 2nd chip, so the entry in the histogram for roc25slot3chip2 is 1 and the entries for the other chips on roc25slot3 are 0. The crates are plotted separately.
CDC total reports: 624000 zero hits: 582645 nonzero hits: 41355 zero/total 93.37 % number of chips reporting 0 hits (582645) / total reports (624000) 93.37 % number of chips reporting 1 hits (27249) / total reports (624000) 4.37 % number of chips reporting 2 hits (8665) / total reports (624000) 1.39 % number of chips reporting 3 hits (3749) / total reports (624000) 0.60 % number of chips reporting 4 hits (1073) / total reports (624000) 0.17 % number of chips reporting 5 hits (378) / total reports (624000) 0.06 % number of chips reporting 6 hits (241) / total reports (624000) 0.04 % 0 hits x 582645 reports = 0 1 hits x 27249 reports = 27249 2 hits x 8665 reports = 17330 3 hits x 3749 reports = 11247 4 hits x 1073 reports = 4292 5 hits x 378 reports = 1890 6 hits x 241 reports = 1446 Total of hits x reports = 63454 Total hits x reports possible = 6 x 624000 = 3744000 Occupancy: total hits x reports / total possible = 1.69 %
FDC total reports: 1560000 zero hits: 1464945 nonzero hits: 95055 zero/total 93.91 % number of chips reporting 0 hits (1464945) / total reports (1560000) 93.91 % number of chips reporting 1 hits (20647) / total reports (1560000) 1.32 % number of chips reporting 2 hits (20342) / total reports (1560000) 1.30 % number of chips reporting 3 hits (20098) / total reports (1560000) 1.29 % number of chips reporting 4 hits (19073) / total reports (1560000) 1.22 % number of chips reporting 5 hits (9508) / total reports (1560000) 0.61 % number of chips reporting 6 hits (5387) / total reports (1560000) 0.35 % 0 hits x 1464945 reports = 0 1 hits x 20647 reports = 20647 2 hits x 20342 reports = 40684 3 hits x 20098 reports = 60294 4 hits x 19073 reports = 76292 5 hits x 9508 reports = 47540 6 hits x 5387 reports = 32322 Total of hits x reports = 277779 Total hits x reports possible = 6 x 1560000 = 9360000 Occupancy: total hits x reports / total possible = 2.97 %
Run 11437, 212nA
From the first 1000 events in run 11437 file 001, 50 um diamond, PERP, 1200A solenoid, 212 nA beam.
Average occupancy is 2% (CDC) and 3% (FDC), details below.
Chip occupancy calculation for CDC: Data file contains 624,000 entries, one for each of 4 crates x 13 boards x 12 chips per board x 1000 events. Total # hits possible = 6 * 624,000. ((1*26912)+(2*9258)+(3*3968)+(4*1067)+(5*324)+(6*210))/(6*624000.0) = 1.72e-02 so this is an average of 1.7% occupancy.
CDC total reports: 624000 zero hits: 582261 nonzero hits: 41739 zero/total 93.31 % number of chips reporting 0 hits (582261) / total reports (624000) 93.31 % number of chips reporting 1 hits (26912) / total reports (624000) 4.31 % number of chips reporting 2 hits (9258) / total reports (624000) 1.48 % number of chips reporting 3 hits (3968) / total reports (624000) 0.64 % number of chips reporting 4 hits (1067) / total reports (624000) 0.17 % number of chips reporting 5 hits (324) / total reports (624000) 0.05 % number of chips reporting 6 hits (210) / total reports (624000) 0.03 % 0 hits x 582261 reports = 0 1 hits x 26912 reports = 26912 2 hits x 9258 reports = 18516 3 hits x 3968 reports = 11904 4 hits x 1067 reports = 4268 5 hits x 324 reports = 1620 6 hits x 210 reports = 1260 Total of hits x reports = 64480 Total hits x reports possible = 6 x 624000 = 3744000 Occupancy: total hits x reports / total possible = 1.72 %
FDC total reports: 1560000 zero hits: 1450179 nonzero hits: 109821 zero/total 92.96 % number of chips reporting 0 hits (1450179) / total reports (1560000) 92.96 % number of chips reporting 1 hits (24417) / total reports (1560000) 1.57 % number of chips reporting 2 hits (23508) / total reports (1560000) 1.51 % number of chips reporting 3 hits (22542) / total reports (1560000) 1.45 % number of chips reporting 4 hits (21734) / total reports (1560000) 1.39 % number of chips reporting 5 hits (10848) / total reports (1560000) 0.70 % number of chips reporting 6 hits (6772) / total reports (1560000) 0.43 % 0 hits x 1450179 reports = 0 1 hits x 24417 reports = 24417 2 hits x 23508 reports = 47016 3 hits x 22542 reports = 67626 4 hits x 21734 reports = 86936 5 hits x 10848 reports = 54240 6 hits x 6772 reports = 40632 Total of hits x reports = 320867 Total hits x reports possible = 6 x 1560000 = 9360000 Occupancy: total hits x reports / total possible = 3.43 %
More runs and innermost CDC rings
| Run | beam current | CDC chip occupancy | CDC rings 1-4 chip occupancy | FDC chip occupancy | |
|---|---|---|---|---|---|
| 11634 file 001 | 42nA | 1.4 % | 4.8 % | 2.6% | |
| 11635 file 010 | 75nA | 1.6% | 5.7% | 2.8% | |
| 11637 file 015 | 112nA | 1.9% | 6.7% | 3.0% | |
| 11636 file 001 | 140nA | 2.1 % | 7.5 % | 3.2% |
| Run | beam current | CDC chip occupancy | CDC rings 1-4 chip occupancy | FDC chip occupancy | |
|---|---|---|---|---|---|
| 11359 file 001 | 202nA | 2.0% | 7.5% | 3.5% | |
| 11360 file 010 | 245nA | 2.2% | 8.2% | 3.7% | |
| 11361 file 001 | 313nA | 2.4 % | 9.1 % | 3.9% | Mean beam current in mystats is 304nA |
| 11362 file 001 | 359nA | 2.7 % | 10.2 % | 4.0% | Mean beam current in mystats is 354nA |
| 11363 file 002 | 412nA | 2.8% | 10.8% | 4.2% |
Average chip occupancy vs beam current:
The CDC lines are for the whole chamber (smaller) and the inmost 4 rings (larger). The FDC lines are for average over all 4 packages. The highest average occupancy for any one FDC chip in run 11363 was 16%, followed by 3 chips with 10-11%, and then many at 9% and below. The occupancy was calculated as total number of hits/number of hits possible, where total is the sum over all chips considered and all events.
