FADC Data Format Mar 25, 2014

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Location and Time

Room: CC F226

Time: 1:30pm-2:30pm

Remote Connection

ESNet: 8542553

(if problems, call phone in conference room: 757-269-6460)


Useful Links


Attendees: David L.(chair), Cody D., Naomi J., Beni Z.

  • Errors due to system clock running at 80MHz
  • Many problems resolved by reducing to 40MHz
  • Could increase some, but it will take a little more work
  • All FDC and CDC modules are installed and tested in Raw mode
    • CDC not installed yet so not reading out anything from it
  • Beni would like to have a firmware version that reads out 170 samples in the window
    • Cody will work on getting a firmware version with registers that allow Beni to set window width and offset
    • This won't really be needed before the CDC is hooked up (couple of weeks?)
  • We need to confirm how many samples are used for pedestal in the f250 firmware and where this number as well as the number used for the integral are stored.
  • Beni noted that previously, he'd observed 50MHz noise
    • In order to minimize affect, the pedestal and integral should have a width that is close to an integral number of the characteristic wavelength.
    • If we integrate 8 samples, that would be 64 ns or 1.5 wavelengths (i.e. optimally bad)
  • Naomi sent a C++ version of her timing algorithm to Mike (?)
    • Discovered one small error in the VHDL code in the process and sent an fixed version to Cody
  • Naomi continues the Garfield calculations and will report in more detail in the future
    • 400 MeV/c protons at 23o