FADC Data Format November 11, 2014
Location and Time
Room: CC F228
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- Previous meeting (Oct 14, 2014)
- Status of FADC125 Firmware
- Readout of integration period for pedestal subtraction
- fADC125 Data Format Specification Document
- Data format for 250 modes on fADC125 from Cody, Aug 15 2014
- FA250 modes 2 from Ed and Hai, Feb 18 2014
- FIRMWARE for FADC250 Ver2 ADC FPGA, Sept 2014?
- CMU timing algorithm - details updated
- CDC readout needs Garfield calcs
Present: Curtis, Naomi (CMU), Cody, Beni, David (JLab)
- FADC125 status
- Cody has resumed work on the new FA125 algorithm, he rebuilt his simulation using Naomi's latest code with several (~9) pulse samples and obtains the same results as Naomi. He added 16 samples of fake pedestal data to the start of the signals.
- The number of samples used for the local pedestal cannot be greater than the number used for the initial pedestal.
- This number will be stored in a register, so it can be increased to 32 if necessary.
- Next he will add registers to store the threshold settings.
- Naomi will send him her C++ data-analyzer code. [done]
- Following David's observation at a previous meeting that the number of samples used for the integral would not be known, Naomi modified the code so that the timing algorithm sums the samples between the leading-edge time determined and the initial threshold crossing (this is the 'latest code' mentioned above). The integration module will sum from the initial threshold crossing to the end of the integration window, and the total number of samples can be determined from the difference between the time of the end of the window and the hit time.
- Naomi spotted 2 mistakes in the format document, table 4(3) and will correct them.
- Cody is checking that possible error conditions are covered.