Difference between revisions of "FADC FPGA Programming Jan 14, 2014"
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** [[Image:20140110_fadc125_schedule.png|100px]] | ** [[Image:20140110_fadc125_schedule.png|100px]] | ||
* [[CDC_algo_status#Implemented_in_VHDL_using_ISE.2C_ISIM_and_XST... | CDC algo status ]] | * [[CDC_algo_status#Implemented_in_VHDL_using_ISE.2C_ISIM_and_XST... | CDC algo status ]] | ||
| − | * Quality factors and data format | + | * Quality factors and data format |
** Quality factors: pedestal, overflow sample count (up to a limit), flags from timing algo (low gradient, inaccurate time?) | ** Quality factors: pedestal, overflow sample count (up to a limit), flags from timing algo (low gradient, inaccurate time?) | ||
=Minutes= | =Minutes= | ||
''TBD'' | ''TBD'' | ||
Revision as of 14:26, 14 January 2014
Location and Time
Room: CC F326-327
Time: 1:30pm-2:30pm
Remote Connection
ESNet: 8542553
(if problems, call phone in conference room: 757-269-6460)
Agenda
- Previous meeting (Dec. 17, 2013)
- fADC125 Data Format Specification Document
- fADC125 version 1 schedule
-
- CDC algo status
- Quality factors and data format
- Quality factors: pedestal, overflow sample count (up to a limit), flags from timing algo (low gradient, inaccurate time?)
Minutes
TBD
