Revision as of 12:38, 21 January 2014

Location and Time

Room: CC F326-327

Time: 1:30pm-2:30pm

Remote Connection

ESNet: 8542553

(if problems, call phone in conference room: 757-269-6460)

Agenda

• Previous meeting (Dec. 17, 2013)
• fADC125 Data Format Specification Document
• fADC125 version 1 schedule
  • 
• CDC algo status
• Quality factors and data format
  • Quality factors: pedestal, overflow sample count (up to a limit), flags from timing algo (low gradient, inaccurate time?)

Minutes

Attendees: David L., Elton S., Cody D., Fernando B., Ed J., Chris C., Curtis M., Naomi J., Beni Z., Hai D.

We discussed the current status of the FADC125 and the possibility of updating the FADC250 data format in the future. Consensus was reached on the time scale and procedure for updating the FADC250.

• Full crate testing of FADC125 modules comes first
  • Full crate tests will be done with the v0 FPGA program that only reads out full waveforms
  • Some software is needed to push the firmware to all modules in create via VME. (Currently it is done a single module at a time.)
  • Cody is working on getting that software from the appropriate local experts.
• Expect the FADC250 algorithms to be working in the FADC125 approx. summer 2014. This will be v1 of the FADC125 FPGA program.
• v2 of FADC250/FADC125 FPGA program:
  • Work will continue from Hall-D end to complete document specifying the desired data format.
  • This may include Naomi's alternate timing algorithm (pending further tests)
  • Plan is to have full discussion draft by beginning of March.
  • Fast electronics group will review and discuss so that a final specification document is completed by summer 2014.
  • Work will then be scheduled to implement v2 program in time for first data taking in Hall-D scheduled for 2015.

In addition, Naomi presented the status of the timing algorithm she has been working on. The original algorithm was developed on waveform data taken with the FADC125v0. She has since worked to implement the algorithm in an FPGA program which she has been able to synthesize and simulate. The timing of the program has a min. clock speed of 7.6 ns that is within spec, but it uses a lot of resources on the FPGA so it must be merged with other parts to see if there is a resource issue. There was also some discussion on how her algorithm as implemented on the FPGA compares to the algorithm already implemented on the FADC250 compares. Naomi was going to have a look at applying both algorithms to the same waveform data in order to make a direct comparison.