Difference between revisions of "FADC algorithm"

Revision as of 16:13, 30 July 2013

A first proposal of a generic algorithm to determine the charge and pedestal (not time). Consider first that the hardware has the following feature:

• The ADC has 72 channels with 12 first order FPGAs, that meas each FPGA handles 6 channels
• Because every other channel is directed to a masoning board no neighboring channels are within any given FPGA. For example channels 0,2,4,6,8,10 are in the first FPGA located on the main board, channels 1,3,5,7,9,11 are in the first FPGA on the masoning board.
• There is a 13th secondary FPGA that will receive data from the 12 primary FPGAs.

Here we consider first how to determine the pedestal and the charge integral:

• Because there is a direct correlation between the trigger time (at the ADC) and the first possible time a real signal belonging to the trigger can happen the region before any signal is known and can be used to determine a pedestal. This region should be set/initialized by 2 parameter that can be configured.
• To determine the charge integral two strategies can be followed.
  1. Simple integrate over a time window regardless of the timing of the signal (acts like any old style charge integrating ADC) with the window size and location set by two parameters during initialization like the pedestal ones.
  2. Determine the earliest time/sample over a threshold from any of the 6 input channels to the FPGA and integrate each channel around this found earliest time with a window given by parameters that can be set during initialization.