Difference between revisions of "FADC algorithm"
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*# Determine the earliest time/sample over a threshold from any of the 6 input channels to the FPGA and integrate each channel around this found earliest time with a window given by parameters that can be set during initialization. | *# Determine the earliest time/sample over a threshold from any of the 6 input channels to the FPGA and integrate each channel around this found earliest time with a window given by parameters that can be set during initialization. | ||
** Note that in both cases the pedestal determined previously should be subtracted and maybe even some bit reduction done such that the integral value fits fine withing the 16 bits we allocate for it. In case that a previous signal has its tail significantly inside the region of the pedestal window and offline correction can easily be applied by comparing the current pedestal to the mean pedestal of accumulated events. | ** Note that in both cases the pedestal determined previously should be subtracted and maybe even some bit reduction done such that the integral value fits fine withing the 16 bits we allocate for it. In case that a previous signal has its tail significantly inside the region of the pedestal window and offline correction can easily be applied by comparing the current pedestal to the mean pedestal of accumulated events. | ||
| − | * The values for Pedestal, Integral and Time(not discussed here) for all 6 channels are then shipped to the secondary FPGA that collects all the data from all FPGAs. Note that only those FPGAs have data if one the 6 channels was over threshold in case of option | + | * The values for Pedestal, Integral and Time(not discussed here) for all 6 channels are then shipped to the secondary FPGA that collects all the data from all FPGAs. Note that only those FPGAs have data if one the 6 channels was over threshold in case of option 2.) and all FPGAs have data in case of option 1.) |
* The secondary FPGA applies a threshold (much lower than the first threshold of option 1.)) and discards all data that has integral values below this | * The secondary FPGA applies a threshold (much lower than the first threshold of option 1.)) and discards all data that has integral values below this | ||
threshold. In this way we retain small energy depositions that are below threshold in the first stage(FPGA) and have no timing signal. | threshold. In this way we retain small energy depositions that are below threshold in the first stage(FPGA) and have no timing signal. | ||
Revision as of 16:29, 30 July 2013
A first proposal of a generic algorithm to determine the charge and pedestal (not time). Consider first that the hardware has the following feature:
- The ADC has 72 channels with 12 first order FPGAs, that meas each FPGA handles 6 channels
- Because every other channel is directed to a masoning board no neighboring channels are within any given FPGA. For example channels 0,2,4,6,8,10 are in the first FPGA located on the main board, channels 1,3,5,7,9,11 are in the first FPGA on the masoning board.
- There is a 13th secondary FPGA that will receive data from the 12 primary FPGAs.
Here we consider first how to determine the pedestal and the charge integral:
- Because there is a direct correlation between the trigger time (at the ADC) and the first possible time a real signal belonging to the trigger can happen the region before any signal is known and can be used to determine a pedestal. This region should be set/initialized by 2 parameter that can be configured.
- To determine the charge integral one of two strategies could be followed.
- Simple integrate over a time window regardless of the timing of the signal (acts like any old style charge integrating ADC) with the window size and location set by two parameters during initialization like the pedestal ones.
- Determine the earliest time/sample over a threshold from any of the 6 input channels to the FPGA and integrate each channel around this found earliest time with a window given by parameters that can be set during initialization.
- Note that in both cases the pedestal determined previously should be subtracted and maybe even some bit reduction done such that the integral value fits fine withing the 16 bits we allocate for it. In case that a previous signal has its tail significantly inside the region of the pedestal window and offline correction can easily be applied by comparing the current pedestal to the mean pedestal of accumulated events.
- The values for Pedestal, Integral and Time(not discussed here) for all 6 channels are then shipped to the secondary FPGA that collects all the data from all FPGAs. Note that only those FPGAs have data if one the 6 channels was over threshold in case of option 2.) and all FPGAs have data in case of option 1.)
- The secondary FPGA applies a threshold (much lower than the first threshold of option 1.)) and discards all data that has integral values below this
threshold. In this way we retain small energy depositions that are below threshold in the first stage(FPGA) and have no timing signal.
