Difference between revisions of "JLab Module Configuration in CODA"
From GlueXWiki
| Line 13: | Line 13: | ||
'''TI:''' | '''TI:''' | ||
tiInit() | tiInit() | ||
| + | - tiReload() | ||
| + | - tiDisableVXSSignals() | ||
| + | - tiSetClockSource(1) '''CLOCK SWITCHOVER''' | ||
| + | - FiberMeas() | ||
| + | - Reset IODelay (bit 14) | ||
| + | - Sync auto alignment (bit 11) | ||
| + | - Measure Latency (bit 15) | ||
| + | - Fiber delay auto align (bit 13) | ||
| + | - Set user defaults | ||
| + | tiLoadTriggerTable(0) | ||
| + | tiSetTriggerHoldoff(..) | ||
| + | tiSetSyncDelayWidth(..) | ||
| + | tiSetBlockLevel(..) | ||
| + | tiSetEventFormat(..) | ||
| + | tiSetBlockBufferLevel(..) | ||
tiDisableVXSSignals() | tiDisableVXSSignals() | ||
| Line 18: | Line 33: | ||
'''TI:''' | '''TI:''' | ||
tiInit() | tiInit() | ||
| + | - tiReload() | ||
| + | - tiDisableVXSSignals() | ||
| + | - tiSetClockSource(1) '''CLOCK SWITCHOVER''' | ||
| + | - FiberMeas() | ||
| + | - Reset IODelay (bit 14) | ||
| + | - Sync auto alignment (bit 11) | ||
| + | - Measure Latency (bit 15) | ||
| + | - Fiber delay auto align (bit 13) | ||
| + | - Set user defaults | ||
| + | tiLoadTriggerTable(0) | ||
| + | tiSetTriggerHoldoff(..) | ||
| + | tiSetSyncDelayWidth(..) | ||
| + | tiSetBlockLevel(..) | ||
| + | tiSetEventFormat(..) | ||
| + | tiSetBlockBufferLevel(..) | ||
| + | '''fADC250''' | ||
| + | faInit(...) | ||
| + | - Sync = VXS, Trigger = VXS, Clock = Internal | ||
| + | |||
tiDisableVXSSignals() | tiDisableVXSSignals() | ||
Revision as of 09:54, 9 May 2013
In this wiki page, we attempt to outline how JLab Modules are configured and run within each CODA transition and state.
The following presents a table of the evolving global trigger setting in the EEL Electronics Lab.
| CODA Transition | Trigger Supervisor Crate | Global Trigger Crate | Payload Crate |
|---|---|---|---|
| Download |
TI: tiInit() - tiReload() - tiDisableVXSSignals() - tiSetClockSource(1) CLOCK SWITCHOVER - FiberMeas() - Reset IODelay (bit 14) - Sync auto alignment (bit 11) - Measure Latency (bit 15) - Fiber delay auto align (bit 13) - Set user defaults tiLoadTriggerTable(0) tiSetTriggerHoldoff(..) tiSetSyncDelayWidth(..) tiSetBlockLevel(..) tiSetEventFormat(..) tiSetBlockBufferLevel(..) tiDisableVXSSignals() |
TI: tiInit() - tiReload() - tiDisableVXSSignals() - tiSetClockSource(1) CLOCK SWITCHOVER - FiberMeas() - Reset IODelay (bit 14) - Sync auto alignment (bit 11) - Measure Latency (bit 15) - Fiber delay auto align (bit 13) - Set user defaults tiLoadTriggerTable(0) tiSetTriggerHoldoff(..) tiSetSyncDelayWidth(..) tiSetBlockLevel(..) tiSetEventFormat(..) tiSetBlockBufferLevel(..) fADC250 faInit(...) - Sync = VXS, Trigger = VXS, Clock = Internal tiDisableVXSSignals() | |
|
TS: tsInit() - Sets user defaults tsSetTriggerSource(..) tsSet*Input(..) - Enables specific inputs tsSetSyncEventInterval(..) tsSetBlockLevel(..) tsLoadTriggerTable() tsSetTriggerHoldoff(..) tsSetSyncDelayWidth(..) tsSetBlockBufferLevel(..) TD: tdInit() - Sets user defaults. - tdAutoAlignSync() - - Resets IODELAY (bit 14) - - Auto Align P0 Sync (bit 11) tdGSetBlockLevel(..) tdGSetBlockBufferLevel(..) tdAddSlave(..) SD: sdInit() sdSetActiveVmeSlots(..) TS: tsClockReset() - Clock250 Resync (0x22) tsTrigLinkReset() - Disables trigger link (twice) (0x55), Enables trigger link (0x77) | |||
| Prestart | |||
|
TS: tsSyncReset() - SyncReset (0xDD) tsIntConnect(...) - Connects trigger routine as the interrupt/polling service routine. - Sets interrupt level and vector. | |||
| Go | |||
|
TS: tsIntEnable(..) - Enables interrupts or starts polling thread. - Enables trigger source | |||
| End |
TS: tsDisableTriggerSource(1) - Disables all trigger sources tsIntDisable() tsIntDisconnect() | ||
| Pre-Download (after Reset, executed prior to Download) |
TS: | ||
