Difference between revisions of "Minutes-2-23-2012"

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# First package tests [https://halldweb1.jlab.org/elog-halld/FDC/ FDC ELOG] (Beni, Lubomir)
 
# First package tests [https://halldweb1.jlab.org/elog-halld/FDC/ FDC ELOG] (Beni, Lubomir)
 
# Engineering update[http://www.jlab.org/Hall-D/detector/fdc/drawings/NEW_MANIFOLD_ASSY2.png],[http://www.jlab.org/Hall-D/detector/fdc/drawings/NEW_MANIFOLD_ASSY1.png cooling manifold] (Bill)  
 
# Engineering update[http://www.jlab.org/Hall-D/detector/fdc/drawings/NEW_MANIFOLD_ASSY2.png],[http://www.jlab.org/Hall-D/detector/fdc/drawings/NEW_MANIFOLD_ASSY1.png cooling manifold] (Bill)  
# Electronics update (Chris)
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# Electronics update (Nick)
 
# Other
 
# Other
  
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= Minutes =
 
= Minutes =
  
Participants: Bill, Dave, Chris, Mark, Simon, Beni, and Lubomir.   
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Participants: Bill, Dave, Nick, Elton, Mark, Simon, Beni, and Lubomir.   
  
 
== Production ==
 
== Production ==
  
- Dave: wire boards #20 and #21 waiting for electroplating. #22 will be populated soon by Chris. Dave showed pictures how the problem on #23 was fixed:
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- Dave: Deadened the first wire plane of package 3 with the larger diameter using the procedure with increased current and the same time as for the smaller diameter, but adding extra polishing cycle. Working on four cathodes now and on the last wire frame for the third package. One more cathode to finish the package. We estimated that for the
the signal trace on wire #96 had short to ground on the back side of the PCB close to the via. The frame was drilled on the back side through the G10 and Rohacell to reach the board, the trace was disconnected before the via and insulated wire was used to make connection to the other side of the board through the via. Wire frame #13 was given to the  EEFAB people for gluing the traces under the HV caps that de-laminated, but they have sent the board to an outside company. There they decided that the traces have enough strength and soldered the HV caps, all this without our knowledge! Fortunately, after replacing one cap with a solder ball on the back, the dark current is now low enough. The next step was to put epoxy on the caps since they are hanging now on the traces. For that, samples were made to test the dark current change. On one cap we had ~200nA with Scotch-weld and ~400nA with Epon one day after gluing across the cap. Therefor the decision was to put Scotch-weld only on the sides of the caps. Ten caps on the sides of the wire frame were already glued. After making sure the dark current is reasonable we will continue with the rest. Working also the cathodes for the third cell of the third package.
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- Two more electroplating samples were made. One with the original procedure with extra polishing; before using the same procedure all the wires were fine except one. Second sample with increasing the time instead of the current compared to the 6cm-diameter original procedure, and in addition the polishing current was increased to have a ratio of 3 w.r.t electroplating current. Will be waiting for the microscope pictures from Olga to make a decision.     
 
- Two more electroplating samples were made. One with the original procedure with extra polishing; before using the same procedure all the wires were fine except one. Second sample with increasing the time instead of the current compared to the 6cm-diameter original procedure, and in addition the polishing current was increased to have a ratio of 3 w.r.t electroplating current. Will be waiting for the microscope pictures from Olga to make a decision.     

Revision as of 19:27, 23 February 2012

February 23, 2012 FDC meeting

Agenda

  1. Production Construction Tracking (Dave)
    • Production status
    • Testing at Blue Crab (Lubomir)
  2. First package tests FDC ELOG (Beni, Lubomir)
  3. Engineering update[1],cooling manifold (Bill)
  4. Electronics update (Nick)
  5. Other