Difference between revisions of "Minutes-6-10-2010"

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# Electronics  
 
# Electronics  
 
#* fADC125 status (Gerard, Fernando)  
 
#* fADC125 status (Gerard, Fernando)  
−
#* noise/grounding [http://argus.phys.uregina.ca/cgi-bin/private/DocDB/ShowDocument?docid=1543 investigations](Fernando)
+
#* noise/grounding [https://halldweb.jlab.org/doc-private/DocDB/ShowDocument?docid=1543 investigations](Fernando)
 
# Cathode redesign [http://www.jlab.org/Hall-D/detector/fdc/drawings/FoilandAllflex_changes_required.docx Bill's changes proposed on the last meeting] (Bill, Roger)  
 
# Cathode redesign [http://www.jlab.org/Hall-D/detector/fdc/drawings/FoilandAllflex_changes_required.docx Bill's changes proposed on the last meeting] (Bill, Roger)  
 
# Full-scale prototype tests
 
# Full-scale prototype tests
Line 23: Line 23:
  
 
== Production ==         
 
== Production ==         
−
- We discussed only the production planning. Bill with the help of Chuck put the cathode production on the FastTrack. When a pdf version will be available it will be linked to the minutes of this meting. The production of one cathode sandwich  (cathode and ground planes) will take about four days with five people: four techs cutting, gluing, stretching the foil and one electrical tech doing the soldering work.  The second type of cathode sandwich doesn't have a ground plane which makes it by a half day faster, but if assuming the same time we will have 8 days per chamber layer or for 30 layers, 240 days in total.
+
- We discussed only the production planning. Bill with the help of Chuck put the cathode production on the FastTrack. When a pdf version will be available it will be linked to the minutes of this meting. The production of one cathode sandwich  (cathode and ground planes) will take about four days with five people: four techs cutting, gluing, stretching the foil and one electrical tech doing the soldering work.  The second type of cathode sandwich doesn't have a ground plane which makes the production by a half day faster, but if assuming the same time, we will have 8 days per chamber layer or for 30 layers, 240 days in total.
  
−
-Fernando had to go to another meeting, so moved to electronics
+
-Fernando had to go to another meeting, so moving to electronics:
  
 
== Electronics ==
 
== Electronics ==
  
−
-
 
  
−
- Fernando informed us that the DAQ group (Bryan Moffit) is working on the drivers for the fADC125 with LINUX CPU and also for VXWorks. Beni said he would prefer to use the CPU we have now (VXWorks) because if we can have the LINUX one it will be temporary. Eugene suggested buying a LINUX CPU. Beni explained the three CPUs available now are from different companies, the DAQ people are evaluating them and we better wait before buying such a CPU. Fernando will ask Bryan when we may expect the drivers for the VXWorks CPU. By that time we will use the fADC with the Gerard's program.  
+
- According Bryan Moffit, the fADC125 module shows problems when operated above 50 Hz rate. Fernando explained, this is just the initial version of the firmware made by Gerard that we can use for cosmic test. Gerard and Bryan are working to solve the issue.
  
−
- the PR for the PCBs were submitted, expect to have the first article in July and the rest by the end of August.  
+
- Bryan, Beni, and Lubomir connected the fADC125 with the Linux CPU to the FDC and are performing tests since Wednesday using the Gerard's code to read the fADC. The fADC was powered on for already 24 hours without heating problems; initially the temperature goes up to 53ded Celsius and stays there. Lubomir investigated the problem of the delay of the signals from one of the cathode cards w.r.t the anode signals. By swapping card inputs and fADC inputs, it turned out the the delay is caused by one of the pre-amp cards or by its cable. Fernando will look into that. Lubomir is analyzing the data from this second run with fADC. He showed a plot (page 483): vertical (perpendicular to the chamber plane) wire position as reconstructed from the ratio of the cathode signals vs wire number. The vertical position changes by 0.5mm from wire #0 (shortest wire) to wire #20. This issue will be investigated taking more data at different places of the chamber.  
−
     
+
       
−
- Fernando investigated the noise coming from the CAEN HV supply. It radiates rather than transmits through the cables. The strips and wires (mainly the long strips) are picking up that noise. Fernando reduced the noise by re-arranging the ground cable connections. Still two of the cards are showing noise. We discussed if we will have the same problems in the hall, i.e. if the detectors will be picking noise from the same CAEN HV crates that will be used for the FDC and CDC. Fernando explained the HV racks will be far from the detectors, but certainly we have to test this.
+
- Fernando posted doc-1543, linked above, explaining the noise investigations of the FDC prototype. Fernando identified the source that radiates noise: the UPS to which the CAEN HV supply and the gas system are connected. The noise depends on the load, that's why when we disconnect the HV system, the noise disappears. Still, this external noise served as a test of the chamber grounding. Fernando discussed ways to improve the grounding of the pre-amp cards by connecting the board's ground directly to the cathode's ground. Fernando, Bill and Roger discussed possible ways of flapping the cathode foil ground on the back of the g10 to be connected to the pre-amp cards. Fernando mentioned also that the noise on the bottom cathode (of the top layer chamber) was much bigger than the noise on the top cathode. Fernando suspects bad ground somewhere. Bill asked what is the difference in the design electrically between the top and the bottom cathode. Lubomir noted that the ground of the top cathode is connected directly to the ground plane above with 6 common flaps, while the ground of the bottom cathode has no direct connection to the ground plane bellow, it is connected through cables. Bill discussed with Fernando the type of the metal to be used for the cooling line so that it can be used also for grounding the cards.
  
 
== Cathode redesign ==
 
== Cathode redesign ==
  
−
- Not all of the Bill's modifications are implemented: the keep-out circle at 1057mm is not on the print. Fernando said the cathode foil procurement may take longer (because of the sole source) than for the PCBs; this could be a showstopper for the new design prototype and therefore for the production.  
+
- Bill has no more corrections/requirements to the last design. Fernando and Roger will work next week to implement the extra grounding of the cards, as discussed above. The hope is to finalize the cathode design by the end of the next week and then submit a PR.
  
 
== Full-scale prototype test results  ==
 
== Full-scale prototype test results  ==
  
−
- Beni discussed several plots on the FDC log book (page 468), showing the wire coordinates reconstructed from the cathode strips. Resolution is between 0.7 - 1mm. Some of the strips are missing. Certainly in some of the areas the resolution is better. The most likely explanation is the noise. There's also a systematic curving of the wire position; Simon and Beni have seen this effect before and probably it will disappear after calibrating the electronics.Beni also studied the effect of changing the field HV from -500V to -700V with always 2225V on the sense wires (page 477): the maximum drift time gets smaller, but the tail up to 400-500ns is still there. Lubomir explains the tail coming from the tracks close to the field wires: if there are no ion pairs produced close to the line between the wires where the field is strong enough, the electrons will take a long path along the field lines till they rich the sense wire.
+
- Beni had several plots linked above, showing that the chamber efficiency is about 97% +/- few percents. The efficiency was estimated using the tracks from the Indiana chamber,  projected on the FDC. Beni also mentioned that after removing the noise from the UPS, the strip resolution was improved (see the plots above). Further improvement will come after calibrating the gains of the strip channels.  
  
−
- Simon showed new results of his simulations using Garfield and Heed packages (FDC logbook page 469). In the first field configuration with high field voltage, the field lines are  mostly in horizontal direction (between the field and sense wires only). The second configuration is similar to the Beni's measurements with -700V on the field wires and the conclusions are the same. Simon is working on correlating the drift times with the track position. He confirms the tails in the drift time spectra are from tracks close to the wires. We will continue discussing the field configurations on the next meeting.
+
- Lubomir already showed above some results from the second test with the fADC125. The plan is to scan some part of the top layer till Monday using the FADC, changing the positions of the cards, and then continue with the standard tests.
−
 
+
−
- There were problems with the gas control system on Tuesday and Wednesday, it tripped almost every our. Eventually Beni got it working but there's no guaranty how long it will survive.  We hope that before that the most important parts of the new gas system will be delivered. There were also gas problems with the middle layer: the metal gauge gas tube was broken. Lubomir fixed it with putty, but then, without the manometer information, it was difficult to get the middle layer bubbling again. Now all the three layers are bubbling.
+
−
 
+
−
- Lubomir discussed several plots (pages 470-476) showing the resolution along the wires estimated using different information: top and bottom cathodes, top cathodes and wire positions, bottom cathodes and wire positions. The different methods give compatible results of 140-160 microns resolution from a single strip plane. Since two cathode planes will be used to reconstruct the coordinate along the wires, we expect a resolution of as low as 100microns. This is possible because of the common noise subtraction that allows to use the information from 5 adjacent strips.  Lubomir outlined that the fADC is a very powerful device in reducing the noise and therefore it is very important to try to implement similar common noise subtraction procedure in the FPGAs. There were discussions whether such procedure is too complex for the FPGAs. Lubomir will prepare descriptions of the procedures used in his analysis and will discuss them before also on the next meeting with Gerard.
+
−
-->
+

Latest revision as of 17:13, 24 February 2017

June 10, 2010 FDC meeting

Tentative Agenda

  1. Production
  2. Electronics
    • fADC125 status (Gerard, Fernando)
    • noise/grounding investigations(Fernando)
  3. Cathode redesign Bill's changes proposed on the last meeting (Bill, Roger)
  4. Full-scale prototype tests
  5. Other


Minutes

Participants: Bill, Casey, Glenn, Roger, Beni, Chuck, Fernando, Simon, and Lubomir

Production

- We discussed only the production planning. Bill with the help of Chuck put the cathode production on the FastTrack. When a pdf version will be available it will be linked to the minutes of this meting. The production of one cathode sandwich (cathode and ground planes) will take about four days with five people: four techs cutting, gluing, stretching the foil and one electrical tech doing the soldering work. The second type of cathode sandwich doesn't have a ground plane which makes the production by a half day faster, but if assuming the same time, we will have 8 days per chamber layer or for 30 layers, 240 days in total.

-Fernando had to go to another meeting, so moving to electronics:

Electronics

- According Bryan Moffit, the fADC125 module shows problems when operated above 50 Hz rate. Fernando explained, this is just the initial version of the firmware made by Gerard that we can use for cosmic test. Gerard and Bryan are working to solve the issue.

- Bryan, Beni, and Lubomir connected the fADC125 with the Linux CPU to the FDC and are performing tests since Wednesday using the Gerard's code to read the fADC. The fADC was powered on for already 24 hours without heating problems; initially the temperature goes up to 53ded Celsius and stays there. Lubomir investigated the problem of the delay of the signals from one of the cathode cards w.r.t the anode signals. By swapping card inputs and fADC inputs, it turned out the the delay is caused by one of the pre-amp cards or by its cable. Fernando will look into that. Lubomir is analyzing the data from this second run with fADC. He showed a plot (page 483): vertical (perpendicular to the chamber plane) wire position as reconstructed from the ratio of the cathode signals vs wire number. The vertical position changes by 0.5mm from wire #0 (shortest wire) to wire #20. This issue will be investigated taking more data at different places of the chamber.

- Fernando posted doc-1543, linked above, explaining the noise investigations of the FDC prototype. Fernando identified the source that radiates noise: the UPS to which the CAEN HV supply and the gas system are connected. The noise depends on the load, that's why when we disconnect the HV system, the noise disappears. Still, this external noise served as a test of the chamber grounding. Fernando discussed ways to improve the grounding of the pre-amp cards by connecting the board's ground directly to the cathode's ground. Fernando, Bill and Roger discussed possible ways of flapping the cathode foil ground on the back of the g10 to be connected to the pre-amp cards. Fernando mentioned also that the noise on the bottom cathode (of the top layer chamber) was much bigger than the noise on the top cathode. Fernando suspects bad ground somewhere. Bill asked what is the difference in the design electrically between the top and the bottom cathode. Lubomir noted that the ground of the top cathode is connected directly to the ground plane above with 6 common flaps, while the ground of the bottom cathode has no direct connection to the ground plane bellow, it is connected through cables. Bill discussed with Fernando the type of the metal to be used for the cooling line so that it can be used also for grounding the cards.

Cathode redesign

- Bill has no more corrections/requirements to the last design. Fernando and Roger will work next week to implement the extra grounding of the cards, as discussed above. The hope is to finalize the cathode design by the end of the next week and then submit a PR.

Full-scale prototype test results

- Beni had several plots linked above, showing that the chamber efficiency is about 97% +/- few percents. The efficiency was estimated using the tracks from the Indiana chamber, projected on the FDC. Beni also mentioned that after removing the noise from the UPS, the strip resolution was improved (see the plots above). Further improvement will come after calibrating the gains of the strip channels.

- Lubomir already showed above some results from the second test with the fADC125. The plan is to scan some part of the top layer till Monday using the FADC, changing the positions of the cards, and then continue with the standard tests.

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