Difference between revisions of "Minutes-9-23-2010"
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- fADC125 mapping: the 2.6mV/fC card output should map onto 80% of the full scale of the fADC125. Additional decrease of the range down to 60% is acceptable if it is needed | - fADC125 mapping: the 2.6mV/fC card output should map onto 80% of the full scale of the fADC125. Additional decrease of the range down to 60% is acceptable if it is needed | ||
| − | to match the CDC requirements for the fADC125. | + | to match the CDC requirements for the fADC125. |
- Gain for the anode cards: with the present gain of 0.6mV/fC and gas gain of 8x10^4, the wire signals saturate. Since the cards will be used in discriminator mode, | - Gain for the anode cards: with the present gain of 0.6mV/fC and gas gain of 8x10^4, the wire signals saturate. Since the cards will be used in discriminator mode, | ||
| Line 46: | Line 46: | ||
reduce the gain by about a factor of two. Again, this will be problematic with the current version of the card since 0.59mV/fC is the lowest possible gain. Gerard will look into that. | reduce the gain by about a factor of two. Again, this will be problematic with the current version of the card since 0.59mV/fC is the lowest possible gain. Gerard will look into that. | ||
| − | - Other fADC125 requirements: Lubomir investigated the effect of the peaking time on the resolution (page | + | - Other fADC125 requirements: Lubomir investigated the effect of the peaking time on the resolution (page 517). Eugene: very small effect and it is not worth optimizing. |
| + | Gerard expects the resolution with fADC125 to be closer to the one with discriminator and has doubts about this result. For the next meeting, Lubomir will prepare additional plots using other interpolation methods. Gerard: the common noise subtraction is not possible in the FPGA that collects the information from all the channels, because the zero suppression should be done before that in the FPGAs for the individual channels. Lubomir and Gerard will discuss other possibilities for the noise reduction. | ||
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== Engineering == | == Engineering == | ||
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== Full-scale prototype == | == Full-scale prototype == | ||
Revision as of 19:49, 23 September 2010
September 23, 2010 FDC meeting
Tentative Agenda
- Production
- Clean room update
- Electronics
- update (Fernando)
- discussions of the FDC requirements for the pre-amplifiers and fADC125 [FDC requirements],[FDC Log Book, pages 516-517]
- Engineering
- Full-scale prototype
- test update (Beni)
- momentum resolution studies [FDC Log Book, pages 515] (Simon)
- Other
Minutes
Participants: Eugene, Fernando, Beni, Bill, Chris, David, Simon, Gerard (on the phone), and Lubomir.
It was a long (2.5 hours) but productive meeting, half of the time discussing the FDC requirements for the electronins, and the other half - the wire stringing procedure.
Production
- Only good news about Blue Crab, procurement will finalize the contract with AdvanceTEC for the construction of the clean room by the end of the month. The AC for the whole area is being installed now.
Electronics
- Fernando: we have now all the PCB boards (except maybe one set, out of 28, that has to be checked). The contract with the assembly company is awarded.
- Fernando: according to the procurement, the sole source for the cathode foils is out of question. Therefore, Fernando submitted the specifications to be posted on the FedBiz site with a deadline for possible offers of Oct. 13.
- Lubomir started preparing a document explaining the FDC requirements for the pre-amplifiers and flash ADC125. It is based on the tests of the full-scale prototype including with fADC125, and on Garfield simulations. This document linked above contains plots and more details that were discussed.
- Gain of the cathode cards: present value of 2.6mV/fC will work for the FDC. To be safe we specify gain range of 2.0 - 3.2. The problem is that in the current pre-amp design, the next possible gain below 2.6 is 0.91. Lower gains might be needed if the cards generate with 2.6mV/fC. The final decision about the gain can can be made after building and testing one full package of 6 chambers.
- fADC125 mapping: the 2.6mV/fC card output should map onto 80% of the full scale of the fADC125. Additional decrease of the range down to 60% is acceptable if it is needed to match the CDC requirements for the fADC125.
- Gain for the anode cards: with the present gain of 0.6mV/fC and gas gain of 8x10^4, the wire signals saturate. Since the cards will be used in discriminator mode, the saturation doesn't affect the time information that will be recorded with F1TDC. If there are other saturation effects, like increased recovery time, then we need to reduce the gain by about a factor of two. Again, this will be problematic with the current version of the card since 0.59mV/fC is the lowest possible gain. Gerard will look into that.
- Other fADC125 requirements: Lubomir investigated the effect of the peaking time on the resolution (page 517). Eugene: very small effect and it is not worth optimizing. Gerard expects the resolution with fADC125 to be closer to the one with discriminator and has doubts about this result. For the next meeting, Lubomir will prepare additional plots using other interpolation methods. Gerard: the common noise subtraction is not possible in the FPGA that collects the information from all the channels, because the zero suppression should be done before that in the FPGAs for the individual channels. Lubomir and Gerard will discuss other possibilities for the noise reduction.
