Difference between revisions of "Overall trigger timing"
| Line 37: | Line 37: | ||
<tr> | <tr> | ||
| − | <td> | + | <td>296 ns<br></td> |
<td>Tagger MOR reaches final AND logic<br></td> | <td>Tagger MOR reaches final AND logic<br></td> | ||
| − | <td>230 ns + | + | <td>230 ns + 66 ns cable, see [[Tagger trigger timing]]<br></td> |
</tr> | </tr> | ||
<tr> | <tr> | ||
| − | <td> | + | <td>296 ns<br></td> |
<td>discriminator sums reach final AND<br></td> | <td>discriminator sums reach final AND<br></td> | ||
<td>Delayed to match MOR<br></td> | <td>Delayed to match MOR<br></td> | ||
| Line 49: | Line 49: | ||
<tr> | <tr> | ||
| − | <td> | + | <td>315 ns<br></td> |
<td>result of final AND reaches trigger supervisor<br></td> | <td>result of final AND reaches trigger supervisor<br></td> | ||
| − | <td> | + | <td>19 ns a guess through trigger logic<br></td> |
</tr> | </tr> | ||
<tr> | <tr> | ||
| − | <td> | + | <td>360 ns<br></td> |
<td>trigger supervisor L1 accept ready<br></td> | <td>trigger supervisor L1 accept ready<br></td> | ||
<td>45 ns internal to TS<br></td> | <td>45 ns internal to TS<br></td> | ||
| Line 63: | Line 63: | ||
<td>385 ns<br></td> | <td>385 ns<br></td> | ||
<td>gate reaches ADC crate<br></td> | <td>gate reaches ADC crate<br></td> | ||
| − | <td> | + | <td>25 ns a guess, cable plus gate generator plus cable<br></td> |
</tr> | </tr> | ||
| Line 75: | Line 75: | ||
<br><br> | <br><br> | ||
| − | Note that my calculation shows the ADC gate reaching the crate EXACTLY at the same time as the signals. This is not a good situation as any slip in timing cuts off the ADC. | + | Note that my calculation shows the ADC gate reaching the crate EXACTLY at the same time as the signals. This is not a good situation as any slip in timing cuts off the ADC. |
Thus I tentatively conclude the current cabling will NOT work. | Thus I tentatively conclude the current cabling will NOT work. | ||
| − | Two solutions are possible: shorten the MOR delay, or add delay to the ADC signals. The former is far preferable as it only involves one cable, whereas the latter involves 36 cables. But it is not clear how much we can shorten the MOR via a direct fast cable between the tagger and the BCAL trigger crates. | + | Two solutions are possible: shorten the MOR delay, or add delay to the ADC signals. The former is far preferable as it only involves one cable, whereas the latter involves 36 cables. But it is not clear how much we can shorten the MOR via a direct fast cable between the tagger and the BCAL trigger crates. I'm guessing we can get the same length as CLAS, 80 ns, and can save 66 ns since the patch cable will be eliminated. |
I propose we proceed on the former. If the latter becomes necessary there are a few possibilities, including purchase of cables, cutting some of the unused 170 ns in half and installing new ends to give 80 ns delay cables, etc. | I propose we proceed on the former. If the latter becomes necessary there are a few possibilities, including purchase of cables, cutting some of the unused 170 ns in half and installing new ends to give 80 ns delay cables, etc. | ||
| − | |||
==Comments== | ==Comments== | ||
| − | I agree that this will not work. I also agree on the plan of action, in the following priority: 1) Try to shorten MOR, 2) Cut unused | + | I agree that this will not work. I also agree on the plan of action, in the following priority: 1) Try to shorten MOR, 2) Cut unused 170ns cable (if there are enough and if this is ok with folks like Richard) and 3) Purchase new cables. -- Zisis |
| + | |||
| + | 21-Jul...preliminary measurement of the RadPhi cables gives 100 and 300 ns, not 80 and 250 ns. If correct we gain an additional 50 ns delay. If we run a new MOR cable (save 66 ns) we gain a total of over 100 ns. This should be adequate to cover items missing above (patch cables, additional logic delays not accounted for yet, etc). I propose we still plan to run a new MOR cable even if the signal cables are 50 ns longer. -- Elliott | ||
Revision as of 12:04, 21 July 2006
Timing Scheme
From Elliott: Below is my current understanding of the trigger timing for the BCAL test:
| Time |
What |
Comment |
| 0 ns |
electron hits tagger foil |
|
| 115 ns |
photon hits BCAL |
125 ns to alcove, but BCAL is about 10 feet upstream on the platform |
| 215 ns |
BCAL PMT signals reach discriminators |
20 ns in PMT plus 80 ns cable |
| 245 ns |
discriminator sum outputs available |
30 ns a guess, but must be delayed before final AND in any case |
| 296 ns |
Tagger MOR reaches final AND logic |
230 ns + 66 ns cable, see Tagger trigger timing |
| 296 ns |
discriminator sums reach final AND |
Delayed to match MOR |
| 315 ns |
result of final AND reaches trigger supervisor |
19 ns a guess through trigger logic |
| 360 ns |
trigger supervisor L1 accept ready |
45 ns internal to TS |
| 385 ns |
gate reaches ADC crate |
25 ns a guess, cable plus gate generator plus cable |
| 385 ns |
BCAL signals reach ADC crate |
20 ns in PMT plus 250 ns cable plus photon flight time |
Note that my calculation shows the ADC gate reaching the crate EXACTLY at the same time as the signals. This is not a good situation as any slip in timing cuts off the ADC.
Thus I tentatively conclude the current cabling will NOT work.
Two solutions are possible: shorten the MOR delay, or add delay to the ADC signals. The former is far preferable as it only involves one cable, whereas the latter involves 36 cables. But it is not clear how much we can shorten the MOR via a direct fast cable between the tagger and the BCAL trigger crates. I'm guessing we can get the same length as CLAS, 80 ns, and can save 66 ns since the patch cable will be eliminated.
I propose we proceed on the former. If the latter becomes necessary there are a few possibilities, including purchase of cables, cutting some of the unused 170 ns in half and installing new ends to give 80 ns delay cables, etc.
Comments
I agree that this will not work. I also agree on the plan of action, in the following priority: 1) Try to shorten MOR, 2) Cut unused 170ns cable (if there are enough and if this is ok with folks like Richard) and 3) Purchase new cables. -- Zisis
21-Jul...preliminary measurement of the RadPhi cables gives 100 and 300 ns, not 80 and 250 ns. If correct we gain an additional 50 ns delay. If we run a new MOR cable (save 66 ns) we gain a total of over 100 ns. This should be adequate to cover items missing above (patch cables, additional logic delays not accounted for yet, etc). I propose we still plan to run a new MOR cable even if the signal cables are 50 ns longer. -- Elliott
