Difference between revisions of "Overall trigger timing"

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Line 14: Line 14:
 
     <tr>
 
     <tr>
 
       <td>0 ns<br></td>
 
       <td>0 ns<br></td>
−
       <td>electron hits tagger foil<br></td>
+
       <td>Electron hits tagger foil<br></td>
 
       <td><br></td>
 
       <td><br></td>
 
     </tr>
 
     </tr>
Line 20: Line 20:
 
     <tr>  
 
     <tr>  
 
       <td>115 ns<br></td>
 
       <td>115 ns<br></td>
−
       <td>photon hits BCAL<br></td>
+
       <td>Photon hits BCAL<br></td>
 
       <td>125 ns to alcove, but BCAL is about 10 feet upstream on the platform<br></td>
 
       <td>125 ns to alcove, but BCAL is about 10 feet upstream on the platform<br></td>
 
     </tr>
 
     </tr>
  
 
     <tr>  
 
     <tr>  
−
       <td>215 ns<br></td>
+
       <td>235 ns<br></td>
 
       <td>BCAL PMT signals reach discriminators<br></td>
 
       <td>BCAL PMT signals reach discriminators<br></td>
−
       <td>20 ns in PMT plus 80 ns cable<br></td>
+
       <td>20 ns in PMT plus 100 ns cable<br></td>
 
     </tr>
 
     </tr>
  
 
     <tr>  
 
     <tr>  
−
       <td>245 ns<br></td>
+
       <td>265 ns<br></td>
−
       <td>discriminator sum outputs available<br></td>
+
       <td>Discriminator sum outputs available<br></td>
 
       <td>30 ns a guess, but must be delayed before final AND in any case<br></td>
 
       <td>30 ns a guess, but must be delayed before final AND in any case<br></td>
 
     </tr>
 
     </tr>
  
 
     <tr>  
 
     <tr>  
−
       <td>296 ns<br></td>
+
       <td>230 ns<br></td>
−
       <td>Tagger MOR reaches final AND logic<br></td>
+
       <td>Tagger MOR reaches BCAL crates<br></td>
−
       <td>230 ns + 66 ns cable, see [[Tagger trigger timing]]<br></td>
+
       <td>150 ns + 80 ns new fast cable, see [[Tagger trigger timing]]<br></td>
 
     </tr>
 
     </tr>
  
−
    <tr>  
+
  <tr>  
−
       <td>296 ns<br></td>
+
       <td>230 ns<br></td>
−
       <td>discriminator sums reach final AND<br></td>
+
       <td>Discriminator sums available<br></td>
 
       <td>Delayed to match MOR<br></td>
 
       <td>Delayed to match MOR<br></td>
 
     </tr>
 
     </tr>
  
 
     <tr>  
 
     <tr>  
−
       <td>315 ns<br></td>
+
       <td>260 ns<br></td>
−
       <td>result of final AND reaches trigger supervisor<br></td>
+
       <td>Trigger reaches trigger supervisor<br></td>
−
       <td>19 ns a guess through trigger logic<br></td>
+
       <td>Guess 30 ns coincidence logic<br></td>
 
     </tr>
 
     </tr>
  
 
     <tr>  
 
     <tr>  
−
       <td>360 ns<br></td>
+
       <td>305 ns<br></td>
−
       <td>trigger supervisor L1 accept ready<br></td>
+
       <td>L1 accept available at TS<br></td>
−
       <td>45 ns internal to TS<br></td>
+
       <td>45 ns internal trigger supervisor<br></td>
 
     </tr>
 
     </tr>
  
 
     <tr>  
 
     <tr>  
−
       <td>385 ns<br></td>
+
       <td>355 ns<br></td>
−
       <td>gate reaches ADC crate<br></td>
+
       <td>ADC gate active</td>
−
       <td>25 ns a guess, cable plus gate generator plus cable<br></td>
+
       <td>50 ns ADC gate generation, cables to ADC crate, ADC internalbr></td>
 
     </tr>
 
     </tr>
 +
  
 
   <tr>  
 
   <tr>  
−
       <td>385 ns<br></td>
+
       <td>435 ns<br></td>
 
       <td>BCAL signals reach ADC crate<br></td>
 
       <td>BCAL signals reach ADC crate<br></td>
−
       <td>20 ns in PMT plus 250 ns cable plus photon flight time<br></td>
+
       <td>20 ns in PMT plus 300 ns cable plus photon flight time<br></td>
 
     </tr>
 
     </tr>
  
Line 75: Line 76:
  
 
<br><br>
 
<br><br>
−
Note that my calculation shows the ADC gate reaching the crate EXACTLY at the same time as the signals.  This is not a good situation as any slip in timing cuts off the ADC. 
 
  
−
Thus I tentatively conclude the current cabling will NOT work. 
+
The above timing works if we can get less than xxx ns (80 ns is target) between the MOR and the BCAL crates.  If not we will have to add delay to the ADC signals.  If so there are a few possibilities, including purchase of cables, cutting some of the unused 170 ns in half and installing new ends to give 85 ns delay cables, etc.
−
 
+
−
Two solutions are possible:  shorten the MOR delay, or add delay to the ADC signals.  The former is far preferable as it only involves one cable, whereas the latter involves 36 cables.  But it is not clear how much we can shorten the MOR via a direct fast cable between the tagger and the BCAL trigger crates.  I'm guessing we can get the same length as CLAS, 80 ns, and can save 66 ns since the patch cable will be eliminated.
+
−
 
+
−
I propose we proceed on the former.  If the latter becomes necessary there are a few possibilities, including purchase of cables, cutting some of the unused 170 ns in half and installing new ends to give 80 ns delay cables, etc.
+
  
  
 
==Comments==
 
==Comments==
  
 +
(comment below referred to earlier scheme, now superceded...ejw)<br>
 
I agree that this will not work.  I also agree on the plan of action, in the following priority: 1) Try to shorten MOR, 2) Cut unused 170ns cable (if there are enough and if this is ok with folks like Richard) and 3) Purchase new cables.  -- Zisis
 
I agree that this will not work.  I also agree on the plan of action, in the following priority: 1) Try to shorten MOR, 2) Cut unused 170ns cable (if there are enough and if this is ok with folks like Richard) and 3) Purchase new cables.  -- Zisis
  
 
21-Jul...preliminary measurement of the RadPhi cables gives 100 and 300 ns, not 80 and 250 ns.  If correct we gain an additional 50 ns delay.  If we run a new MOR cable (save 66 ns) we gain a total of over 100 ns.  This should be adequate to cover items missing above (patch cables, additional logic delays not accounted for yet, etc).  I propose we still plan to run a new MOR cable even if the signal cables are 50 ns longer.  -- Elliott
 
21-Jul...preliminary measurement of the RadPhi cables gives 100 and 300 ns, not 80 and 250 ns.  If correct we gain an additional 50 ns delay.  If we run a new MOR cable (save 66 ns) we gain a total of over 100 ns.  This should be adequate to cover items missing above (patch cables, additional logic delays not accounted for yet, etc).  I propose we still plan to run a new MOR cable even if the signal cables are 50 ns longer.  -- Elliott
 +
 +
21-Jul...everything updated based on latest understanding -- Elliott

Revision as of 15:41, 21 July 2006

Timing Scheme

From Elliott: Below is my current understanding of the trigger timing for the BCAL test:


Time
 What
 Comment
0 ns
 Electron hits tagger foil
115 ns
 Photon hits BCAL
 125 ns to alcove, but BCAL is about 10 feet upstream on the platform
235 ns
 BCAL PMT signals reach discriminators
 20 ns in PMT plus 100 ns cable
265 ns
 Discriminator sum outputs available
 30 ns a guess, but must be delayed before final AND in any case
230 ns
 Tagger MOR reaches BCAL crates
 150 ns + 80 ns new fast cable, see Tagger trigger timing
230 ns
 Discriminator sums available
 Delayed to match MOR
260 ns
 Trigger reaches trigger supervisor
 Guess 30 ns coincidence logic
305 ns
 L1 accept available at TS
 45 ns internal trigger supervisor
355 ns
 ADC gate active 50 ns ADC gate generation, cables to ADC crate, ADC internalbr>
435 ns
 BCAL signals reach ADC crate
 20 ns in PMT plus 300 ns cable plus photon flight time



The above timing works if we can get less than xxx ns (80 ns is target) between the MOR and the BCAL crates. If not we will have to add delay to the ADC signals. If so there are a few possibilities, including purchase of cables, cutting some of the unused 170 ns in half and installing new ends to give 85 ns delay cables, etc.


Comments

(comment below referred to earlier scheme, now superceded...ejw)
I agree that this will not work. I also agree on the plan of action, in the following priority: 1) Try to shorten MOR, 2) Cut unused 170ns cable (if there are enough and if this is ok with folks like Richard) and 3) Purchase new cables. -- Zisis

21-Jul...preliminary measurement of the RadPhi cables gives 100 and 300 ns, not 80 and 250 ns. If correct we gain an additional 50 ns delay. If we run a new MOR cable (save 66 ns) we gain a total of over 100 ns. This should be adequate to cover items missing above (patch cables, additional logic delays not accounted for yet, etc). I propose we still plan to run a new MOR cable even if the signal cables are 50 ns longer. -- Elliott

21-Jul...everything updated based on latest understanding -- Elliott

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