Difference between revisions of "Overall trigger timing"
| Line 1: | Line 1: | ||
==Timing Scheme== | ==Timing Scheme== | ||
| − | From Elliott: Below is my current understanding of the trigger timing for the BCAL test: | + | From Elliott: Below is my current understanding (4pm 21-Jul-2006) of the trigger timing for the BCAL test: |
| Line 27: | Line 27: | ||
<td>230 ns<br></td> | <td>230 ns<br></td> | ||
<td>Tagger MOR reaches BCAL crates<br></td> | <td>Tagger MOR reaches BCAL crates<br></td> | ||
| − | <td>150 ns + 80 ns new | + | <td>150 ns + 80 ns new cable, see [[Tagger trigger timing]]<br></td> |
</tr> | </tr> | ||
| Line 39: | Line 39: | ||
<td>265 ns<br></td> | <td>265 ns<br></td> | ||
<td>Discriminator sum outputs arrive at trigger logic<br></td> | <td>Discriminator sum outputs arrive at trigger logic<br></td> | ||
| − | <td>30 ns is a guess<br></td> | + | <td>30 ns in discriminators is a guess<br></td> |
</tr> | </tr> | ||
| Line 62: | Line 62: | ||
<tr> | <tr> | ||
<td>390 ns<br></td> | <td>390 ns<br></td> | ||
| − | <td>ADC gate active</td> | + | <td>earliest that ADC gate can be active</td> |
| − | <td>50 ns ADC gate generation, cables to ADC crate, ADC | + | <td>50 ns ADC gate generation, cables to ADC crate, ADC internal<br></td> |
</tr> | </tr> | ||
| Line 76: | Line 76: | ||
<br><br> | <br><br> | ||
| − | The above timing works if we can get less than | + | The above timing works if we can get less than 125 ns between the MOR and the BCAL crates. Note that at 80 ns we need to delay MOR by 35 ns to match the discriminators, so 115 ns should work fine. We may not need a special fast cable between the MOR and BCAL crates, as standard RG58 may suffice if 115 ns is correct. |
| + | |||
| + | If we have to delay the ADC signals there are a few possibilities, including purchase of cables, cutting some of the unused 170 ns in half and installing new ends to give 85 ns delay cables, etc. | ||
Revision as of 16:04, 21 July 2006
Timing Scheme
From Elliott: Below is my current understanding (4pm 21-Jul-2006) of the trigger timing for the BCAL test:
| Time |
What |
Comment |
| 0 ns |
Electron hits tagger foil |
|
| 115 ns |
Photon hits BCAL |
125 ns to alcove, but BCAL is about 10 feet upstream on the platform |
| 230 ns |
Tagger MOR reaches BCAL crates |
150 ns + 80 ns new cable, see Tagger trigger timing |
| 235 ns |
BCAL PMT signals reach discriminators |
20 ns in PMT plus 100 ns cable |
| 265 ns |
Discriminator sum outputs arrive at trigger logic |
30 ns in discriminators is a guess |
| 265 ns |
MOR arrives at trigger logic |
Delayed to match discriminator sum outputs |
| 295 ns |
Trigger reaches trigger supervisor |
Guess 30 ns coincidence logic plus cable |
| 340 ns |
L1 accept available at TS |
45 ns internal trigger supervisor |
| 390 ns |
earliest that ADC gate can be active | 50 ns ADC gate generation, cables to ADC crate, ADC internal |
| 435 ns |
BCAL signals reach ADC crate |
20 ns in PMT plus 300 ns cable plus photon flight time |
The above timing works if we can get less than 125 ns between the MOR and the BCAL crates. Note that at 80 ns we need to delay MOR by 35 ns to match the discriminators, so 115 ns should work fine. We may not need a special fast cable between the MOR and BCAL crates, as standard RG58 may suffice if 115 ns is correct.
If we have to delay the ADC signals there are a few possibilities, including purchase of cables, cutting some of the unused 170 ns in half and installing new ends to give 85 ns delay cables, etc.
Comments
(Zisis' comment referred to am earlier scheme, now superceded...ejw)
I agree that this will not work. I also agree on the plan of action, in the following priority: 1) Try to shorten MOR, 2) Cut unused 170ns cable (if there are enough and if this is ok with folks like Richard) and 3) Purchase new cables. -- Zisis
(my comment also referred to the older scheme, now superceded...ejw)
21-Jul...preliminary measurement of the RadPhi cables gives 100 and 300 ns, not 80 and 250 ns. If correct we gain an additional 50 ns delay. If we run a new MOR cable (save 150 ns) we gain a total of over 100 ns. This should be adequate to cover items missing above (patch cables, additional logic delays not accounted for yet, etc). I propose we still plan to run a new MOR cable even if the signal cables are 50 ns longer. -- Elliott
21-Jul...everything updated based on latest understanding -- Elliott
