Difference between revisions of "Overall trigger timing"

From GlueXWiki
Jump to: navigation, search
(Comments)
 
(13 intermediate revisions by 2 users not shown)
Line 1: Line 1:
Below is my current understanding of the trigger timing for the BCAL test:
+
==Timing Scheme==
 +
 
 +
From Elliott: Below is my current understanding (3pm 22-Sep-2006) of the trigger timing for the BCAL test:
  
  
Line 12: Line 14:
 
     <tr>
 
     <tr>
 
       <td>0 ns<br></td>
 
       <td>0 ns<br></td>
       <td>electron hits tagger foil<br></td>
+
       <td>Electron hits tagger foil<br></td>
 
       <td><br></td>
 
       <td><br></td>
 
     </tr>
 
     </tr>
  
 
     <tr>  
 
     <tr>  
       <td>120 ns<br></td>
+
       <td>115 ns<br></td>
       <td>photon hits BCAL<br></td>
+
       <td>Photon hits BCAL<br></td>
       <td>BCAL is a few feet upstream of alcove<br></td>
+
       <td>125 ns to alcove, but BCAL is about 10 feet upstream on the platform<br></td>
 
     </tr>
 
     </tr>
 +
  
 
     <tr>  
 
     <tr>  
       <td>220 ns<br></td>
+
       <td>235 ns<br></td>
 
       <td>BCAL PMT signals reach discriminators<br></td>
 
       <td>BCAL PMT signals reach discriminators<br></td>
       <td>20 ns in PMT plus 80 ns cable<br></td>
+
       <td>20 ns in PMT plus 100 ns cable<br></td>
 
     </tr>
 
     </tr>
  
 
     <tr>  
 
     <tr>  
       <td>250 ns<br></td>
+
       <td>265 ns<br></td>
       <td>discriminator sum outputs available<br></td>
+
       <td>Discriminator sum outputs arrive at trigger logic<br></td>
       <td>30 ns a guess, but must be delayed before final AND in any case<br></td>
+
       <td>30 ns in discriminators is a guess<br></td>
 
     </tr>
 
     </tr>
  
    <tr>  
+
  <tr>  
       <td>310 ns<br></td>
+
       <td>290 ns<br></td>
       <td>Tagger MOR reaches final AND logic<br></td>
+
       <td>BCAL AND and OR available<br></td>
       <td><br></td>
+
       <td>25 ns is a guess<br></td>
 
     </tr>
 
     </tr>
  
 
     <tr>  
 
     <tr>  
       <td>310 ns<br></td>
+
       <td>290 ns<br></td>
       <td>discriminator sums reach final AND<br></td>
+
       <td>Tagger MOR reaches trigger logic<br></td>
       <td><br></td>
+
       <td>150 ns tagger logic + 138.5 ns new cable, see [[Tagger trigger timing]]<br></td>
 +
    </tr>
 +
 
 +
    <tr>
 +
      <td>320 ns<br></td>
 +
      <td>Trigger reaches trigger supervisor<br></td>
 +
      <td>Guess everything ready 30 ns after MOR<br></td>
 
     </tr>
 
     </tr>
  
 
     <tr>  
 
     <tr>  
       <td>325 ns<br></td>
+
       <td>340 ns<br></td>
       <td>result of final AND reaches trigger supervisor<br></td>
+
       <td>L1 accept available at TS<br></td>
       <td><br></td>
+
       <td>20 ns internal trigger supervisor using prompt mode<br></td>
 
     </tr>
 
     </tr>
  
 
     <tr>  
 
     <tr>  
       <td>370 ns<br></td>
+
       <td>390 ns<br></td>
       <td>internal trigger supervisor<br></td>
+
       <td>earliest that ADC gate can be active</td>
       <td><br></td>
+
       <td>50 ns ADC gate generation, cables to ADC crate, ADC internal<br></td>
 
     </tr>
 
     </tr>
  
 
     <tr>  
 
     <tr>  
       <td>385 ns<br></td>
+
       <td>435 ns<br></td>
       <td>gate reaches ADC crate<br></td>
+
       <td>BCAL signals reach ADC crate<br></td>
       <td><br></td>
+
       <td>20 ns in PMT plus 300 ns cable plus photon flight time<br></td>
 
     </tr>
 
     </tr>
  
 +
</table>
  
 +
<br><br>
  
 +
If the above does not work and we have to delay the ADC signals there are a few possibilities: pulling out 37 unused 100 ns cables from the tray, cutting some of the unused 170 ns in half and installing new ends to give 85 ns delay cables, scrounging up delay boxes, etc.
  
 +
==Comments==
  
</table>
+
(Zisis' comment referred to am earlier scheme, now superceded...ejw)<br>
 +
I agree that this will not work.  I also agree on the plan of action, in the following priority: 1) Try to shorten MOR, 2) Cut unused 170ns cable (if there are enough and if this is ok with folks like Richard) and 3) Purchase new cables.  -- Zisis
 +
 
 +
(my comment also referred to the older scheme, now superceded...ejw)<br>
 +
21-Jul...preliminary measurement of the RadPhi cables gives 100 and 300 ns, not 80 and 250 ns.  If correct we gain an additional 50 ns delay.  If we run a new MOR cable (save 150 ns) we gain a total of over 100 ns.  This should be adequate to cover items missing above (patch cables, additional logic delays not accounted for yet, etc).  I propose we still plan to run a new MOR cable even if the signal cables are 50 ns longer.  -- Elliott
 +
 
 +
21-Jul...everything updated based on latest understanding -- Elliott
 +
 
 +
22-Sep...everything updated based on actual cables and measurements -- Elliott

Latest revision as of 15:24, 22 September 2006

Timing Scheme

From Elliott: Below is my current understanding (3pm 22-Sep-2006) of the trigger timing for the BCAL test:


Time
What
Comment
0 ns
Electron hits tagger foil

115 ns
Photon hits BCAL
125 ns to alcove, but BCAL is about 10 feet upstream on the platform
235 ns
BCAL PMT signals reach discriminators
20 ns in PMT plus 100 ns cable
265 ns
Discriminator sum outputs arrive at trigger logic
30 ns in discriminators is a guess
290 ns
BCAL AND and OR available
25 ns is a guess
290 ns
Tagger MOR reaches trigger logic
150 ns tagger logic + 138.5 ns new cable, see Tagger trigger timing
320 ns
Trigger reaches trigger supervisor
Guess everything ready 30 ns after MOR
340 ns
L1 accept available at TS
20 ns internal trigger supervisor using prompt mode
390 ns
earliest that ADC gate can be active 50 ns ADC gate generation, cables to ADC crate, ADC internal
435 ns
BCAL signals reach ADC crate
20 ns in PMT plus 300 ns cable plus photon flight time



If the above does not work and we have to delay the ADC signals there are a few possibilities: pulling out 37 unused 100 ns cables from the tray, cutting some of the unused 170 ns in half and installing new ends to give 85 ns delay cables, scrounging up delay boxes, etc.

Comments

(Zisis' comment referred to am earlier scheme, now superceded...ejw)
I agree that this will not work. I also agree on the plan of action, in the following priority: 1) Try to shorten MOR, 2) Cut unused 170ns cable (if there are enough and if this is ok with folks like Richard) and 3) Purchase new cables. -- Zisis

(my comment also referred to the older scheme, now superceded...ejw)
21-Jul...preliminary measurement of the RadPhi cables gives 100 and 300 ns, not 80 and 250 ns. If correct we gain an additional 50 ns delay. If we run a new MOR cable (save 150 ns) we gain a total of over 100 ns. This should be adequate to cover items missing above (patch cables, additional logic delays not accounted for yet, etc). I propose we still plan to run a new MOR cable even if the signal cables are 50 ns longer. -- Elliott

21-Jul...everything updated based on latest understanding -- Elliott

22-Sep...everything updated based on actual cables and measurements -- Elliott