Difference between revisions of "Topics for discussion"

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== 1. Overview main features of the GlueX subdetectors  
+
'''<big>1. Overview main features of the GlueX subdetectors which are planned be integrated into the Level-1 trigger:</big>'''
  which are planned be integrated to the Level-1 trigger: ==
+
* Tagger microscope counters
 +
* Start Counter
 +
* FCAL
 +
* BCAL
 +
* TOF
 +
<u>Discuss</u>:
 +
:#  feasibility of usage and their role in the Level-1 algorithm,
 +
:#    rates induced by electromagnetic and hadronic interactions,
 +
:#    signal responses: pulse shapes and signal propagation timing
 +
:#:    (feedback is needed from the prototypes test: BCAL, TOF)
 +
:#    signal thresholds,
 +
:#    cabling.
  
    - Tagger microscope counters
 
    - Start Counter
 
    - FCAL
 
    - BCAL
 
    - TOF
 
  
Discuss:
+
'''<big>2. Overview the trigger algorithm.</big>'''
        - feasibility of usage, their role in the Level-1 algorithm,
+
        - rates induced by electromagnetic and hadronic interactions,
+
        - signal responses: pulse shapes and signal propagation timing
+
          (feedback is needed from the prototypes test: BCAL, TOF)
+
        - signal thresholds,
+
        - cabling.
+
  
2. Overview the trigger algorithm.
 
  
 +
'''<big>3. Trigger types</big>'''
 +
*:  global self-triggered types (physics, cosmics, random, calibration ...),
 +
*:  external triggers (calibration), and sub-detector standalone triggers 
 +
*:<u>Feedback is needed from sub-detector and calibration groups.</u>
  
3. Trigger types.
 
  - global self-triggered types (physics, cosmics, random, calibration ...),
 
    external triggers (calibration), and sub-detector standalone triggers 
 
 
 
Feedback is needed from sub-detector and calibration groups.
 
  
 +
'''<big> 4. Overview trigger electronics</big>:
 +
* <u>Performance of board prototypes:</u>
 +
*# fADC250 (modes, FPGA resources...)
 +
*# Signal Distribution      (SD) 
 +
*# Trigger Interface        (TI)
 +
*# Crate Trigger Processor  (CTP)
 +
*# Results from the 2 crates test stand
  
4. Overview trigger electronics:
+
* <u>Specifications (design) of the board prototypes:</u>
 +
*# Sub-System processor      (SSP)
 +
*# Trigger Distribution      (TD)
 +
*# Trigger Supervisor        (TS)
 +
*# Global Trigger Processor  (GTP)
  
Performance of board prototypes:
 
  - F1ADC (modes, FPGA resources...)
 
  - Signal Distribution      (SD) 
 
  - Trigger Interface        (TI)
 
  - Crate Trigger Processor  (CTP)
 
  - Results from the 2 crates test stand
 
  
Specifications (design) of the board prototypes:
+
'''<big>5. Monitoring of the hardware performance </big>
  - Sub-System processor      (SSP)
+
:# Online monitors ( scalers )
  - Trigger Distribution      (TD)
+
:# Algorithm/hardware tests using inputs from MC simulation
  - Trigger Supervisor        (TS)
+
  - Global Trigger Processor  (GTP)
+
  
  
5. Monitoring of the hardware performance
+
'''<big>6. Trigger electronics in 12 GeV HALL-B project </big>
  - Online monitors ( scalers )
+
  - algorithm/hardware test using inputs from MC simulation
+

Latest revision as of 08:58, 3 June 2009

1. Overview main features of the GlueX subdetectors which are planned be integrated into the Level-1 trigger:

  • Tagger microscope counters
  • Start Counter
  • FCAL
  • BCAL
  • TOF

Discuss:

  1. feasibility of usage and their role in the Level-1 algorithm,
  2. rates induced by electromagnetic and hadronic interactions,
  3. signal responses: pulse shapes and signal propagation timing
    (feedback is needed from the prototypes test: BCAL, TOF)
  4. signal thresholds,
  5. cabling.


2. Overview the trigger algorithm.


3. Trigger types

  • global self-triggered types (physics, cosmics, random, calibration ...),
    external triggers (calibration), and sub-detector standalone triggers
    Feedback is needed from sub-detector and calibration groups.


4. Overview trigger electronics:

  • Performance of board prototypes:
    1. fADC250 (modes, FPGA resources...)
    2. Signal Distribution (SD)
    3. Trigger Interface (TI)
    4. Crate Trigger Processor (CTP)
    5. Results from the 2 crates test stand
  • Specifications (design) of the board prototypes:
    1. Sub-System processor (SSP)
    2. Trigger Distribution (TD)
    3. Trigger Supervisor (TS)
    4. Global Trigger Processor (GTP)


5. Monitoring of the hardware performance

  1. Online monitors ( scalers )
  2. Algorithm/hardware tests using inputs from MC simulation


6. Trigger electronics in 12 GeV HALL-B project