Difference between revisions of "Topics for discussion"

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== 1. Overview main features of the GlueX subdetectors  
+
#'''<big> Overview main features of the GlueX subdetectors which are planned be integrated into the Level-1 trigger:</big>'''
  which are planned be integrated to the Level-1 trigger: ==
+
#* Tagger microscope counters
 +
#* Start Counter
 +
#* FCAL
 +
#* BCAL
 +
#* TOF
 +
#:<u>Discuss</u>:
 +
##  feasibility of usage and their role in the Level-1 algorithm,
 +
##    rates induced by electromagnetic and hadronic interactions,
 +
##    signal responses: pulse shapes and signal propagation timing
 +
##:    (feedback is needed from the prototypes test: BCAL, TOF)
 +
##    signal thresholds,
 +
##    cabling.
  
    - Tagger microscope counters
 
    - Start Counter
 
    - FCAL
 
    - BCAL
 
    - TOF
 
  
Discuss:
+
# '''<big>Overview the trigger algorithm.</big>'''
        - feasibility of usage, their role in the Level-1 algorithm,
+
        - rates induced by electromagnetic and hadronic interactions,
+
        - signal responses: pulse shapes and signal propagation timing
+
          (feedback is needed from the prototypes test: BCAL, TOF)
+
        - signal thresholds,
+
        - cabling.
+
  
2. Overview the trigger algorithm.
+
#'''<big>Trigger types</big>'''
 +
#:  global self-triggered types (physics, cosmics, random, calibration ...),
 +
#:  external triggers (calibration), and sub-detector standalone triggers 
 +
#:<u>Feedback is needed from sub-detector and calibration groups.</u>
  
  
3. Trigger types.
+
'''<big> 4. Overview trigger electronics</big>:
  - global self-triggered types (physics, cosmics, random, calibration ...),
+
* <u>Performance of board prototypes:</u>
    external triggers (calibration), and sub-detector standalone triggers  
+
*# F1ADC (modes, FPGA resources...)
    
+
*# Signal Distribution      (SD)   
Feedback is needed from sub-detector and calibration groups.
+
*# Trigger Interface        (TI)
 +
*# Crate Trigger Processor   (CTP)
 +
*# Results from the 2 crates test stand
  
 
+
* <u>Specifications (design) of the board prototypes:</u>
4. Overview trigger electronics:
+
*# Sub-System processor      (SSP)
 
+
*# Trigger Distribution      (TD)
Performance of board prototypes:
+
*# Trigger Supervisor        (TS)
  - F1ADC (modes, FPGA resources...)
+
*# Global Trigger Processor  (GTP)
  - Signal Distribution      (SD) 
+
  - Trigger Interface        (TI)
+
  - Crate Trigger Processor  (CTP)
+
  - Results from the 2 crates test stand
+
 
+
Specifications (design) of the board prototypes:
+
  - Sub-System processor      (SSP)
+
  - Trigger Distribution      (TD)
+
  - Trigger Supervisor        (TS)
+
  - Global Trigger Processor  (GTP)
+
  
  

Revision as of 15:58, 1 June 2009

  1. Overview main features of the GlueX subdetectors which are planned be integrated into the Level-1 trigger:
    • Tagger microscope counters
    • Start Counter
    • FCAL
    • BCAL
    • TOF
    Discuss:
    1. feasibility of usage and their role in the Level-1 algorithm,
    2. rates induced by electromagnetic and hadronic interactions,
    3. signal responses: pulse shapes and signal propagation timing
      (feedback is needed from the prototypes test: BCAL, TOF)
    4. signal thresholds,
    5. cabling.


  1. Overview the trigger algorithm.
  1. Trigger types
    global self-triggered types (physics, cosmics, random, calibration ...),
    external triggers (calibration), and sub-detector standalone triggers
    Feedback is needed from sub-detector and calibration groups.


4. Overview trigger electronics:

  • Performance of board prototypes:
    1. F1ADC (modes, FPGA resources...)
    2. Signal Distribution (SD)
    3. Trigger Interface (TI)
    4. Crate Trigger Processor (CTP)
    5. Results from the 2 crates test stand
  • Specifications (design) of the board prototypes:
    1. Sub-System processor (SSP)
    2. Trigger Distribution (TD)
    3. Trigger Supervisor (TS)
    4. Global Trigger Processor (GTP)


5. Monitoring of the hardware performance

  - Online monitors ( scalers )
  - algorithm/hardware test using inputs from MC simulation