Content:
#
# fadc250 config file - EXAMPLE
#
# this file contains settings for
# fADC250 - JLAB VXS Flash ADC 12-bit 250 Msps 16 ch
#
# format:
# ~~~~~~~
# CRATE rocbcal1 <- ROC name, crate name, usually IP name
# FADC250_ALLSLOTS <- just keyword - all settings after this line will be implemented
# for all slots, till FADC250_SLOTS will be met
# FADC250_SLOTS 3 8 15 <- slot_numbers - in which next settings will be implemented
# till file ends or next FADC250_SLOTS will be met
#
# FADC250_F_REV 0x0216 <- firmware revision (0x0 Bits:7-0)
# FADC250_B_REV 0x0908 <- board revision (0x0 Bits:15-8)
# FADC250_ID 0xfadc <- board type (0x0 Bits:31-16)
#
# FADC250_MODE 1 <- process mode: 1-4 (0x10C Bits:2-0)
# FADC250_W_OFFSET 50 <- number of sample back from trigger point. (0x120)
# (in Manual it is PL=Trigger_Window(ns) * 250MHz)
# FADC250_W_WIDTH 49 <- number of ADC sample to include in trigger window. (0x11C)
# (in M: PTW=Trigger_Window(ns) * 250MHz, minimum is 6)
# FADC250_NSB 3 <- number of sample before trigger point to include in data processing. (0x124)
# This include the trigger Point. (minimum is 2 in all mode)
# FADC250_NSA 6 <- number of sample after trigger point to include in data processing. (0x128)
# Minimum is (6 in mode 2) and ( 3 in mode 0 and 1).
# Number of sample report is 1 more for odd and 2 more for even NSA number.
# FADC250_NPEAK 1 <- number of Pulses in Mode 2 and 3. (0x10C Bits:6-5)
#
# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - channels ##
# FADC250_ADC_MASK 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 <- channel enable mask (0x110)
# FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- trigger enable mask
# (channel includes in global trigger, if bit set to 1)
# FADC250_TET 110 <- board Trigger Energy Threshold (TET), same for all 16 channels
# FADC250_CH_TET 0 110 <- channel# and TET_value for this channel
# FADC250_ALLCH_TET 111 222 2 3 4 5 6 7 8 9 10 11 12 13 14 15 <- 16 TETs (0x12C - 0x148)
#
# FADC250_DAC 3300 <- board DAC, one and the same for all 16 channels
# FADC250_CH_DAC 0 3300 <- channel# and DAC_value for this channel
# FADC250_ALLCH_DAC 3300 3280 3310 3280 3310 3280 3310 3280 3300 3280 3300 3280 3310 3280 3310 3280 <- 16 DACs
#
# FADC250_PED 210 <- board Pedestals, same for all channels
# FADC250_CH_PED 0 210 <- channel# and Pedestal_value for this channel
# FADC250_ALLCH_PED 210 220 210 215 215 220 220 210 210 215 215 220 220 210 215 220 <- 16 PEDs
CRATE rocfcal8
############################
FADC250_SLOTS 3
#########################
FADC250_ALLCH_DAC 3390 3382 3355 3383 3356 3385 3376 3375 3358 3374 3357 3400 3404 3368 3397 3365
############################
FADC250_SLOTS 4
#########################
FADC250_ALLCH_DAC 3382 3351 3364 3362 3377 3388 3360 3373 3357 3377 3365 3356 3379 3380 3370 3390
############################
FADC250_SLOTS 5
#########################
FADC250_ALLCH_DAC 3387 3383 3360 3376 3363 3365 3376 3371 3370 3344 3370 3381 3382 3352 3361 3374
############################
FADC250_SLOTS 6
#########################
FADC250_ALLCH_DAC 3382 3329 3368 3397 3378 3346 3338 3360 3370 3392 3336 3381 3360 3338 3346 3360
############################
FADC250_SLOTS 7
#########################
FADC250_ALLCH_DAC 3380 3366 3391 3388 3386 3375 3367 3376 3383 3389 3377 3354 3365 3380 3388 3364
############################
FADC250_SLOTS 8
#########################
FADC250_ALLCH_DAC 3361 3345 3380 3374 3357 3400 3363 3384 3356 3358 3358 3382 3381 3363 3334 3349
############################
FADC250_SLOTS 9
#########################
FADC250_ALLCH_DAC 3395 3360 3359 3382 3382 3380 3391 3382 3373 3378 3352 3349 3383 3366 3360 3339
############################
FADC250_SLOTS 10
#########################
FADC250_ALLCH_DAC 3364 3357 3354 3366 3351 3367 3356 3358 3345 3370 3368 3355 3339 3360 3352 3355
############################
FADC250_SLOTS 13
#########################
FADC250_ALLCH_DAC 3395 3383 3392 3382 3363 3355 3372 3393 3407 3382 3405 3379 3382 3383 3375 3373
############################
FADC250_SLOTS 14
#########################
FADC250_ALLCH_DAC 3369 3368 3344 3363 3364 3376 3360 3371 3365 3357 3363 3379 3349 3371 3352 3371
############################
FADC250_SLOTS 15
#########################
FADC250_ALLCH_DAC 3359 3365 3357 3376 3372 3399 3364 3367 3356 3368 3354 3383 3353 3361 3371 3355
############################
FADC250_SLOTS 16
#########################
FADC250_ALLCH_DAC 3368 3346 3346 3357 3378 3343 3364 3376 3375 3379 3333 3370 3363 3369 3356 3351
############################
FADC250_SLOTS 17
#########################
FADC250_ALLCH_DAC 3384 3358 3367 3387 3363 3366 3366 3369 3362 3357 3355 3403 3385 3390 3367 3368
############################
FADC250_SLOTS 18
#########################
FADC250_ALLCH_DAC 3378 3349 3352 3351 3373 3398 3371 3388 3381 3380 3349 3389 3363 3381 3360 3374
############################
FADC250_SLOTS 19
#########################
FADC250_ALLCH_DAC 3366 3380 3367 3376 3368 3353 3352 3397 3373 3351 3362 3363 3369 3341 3356 3363