Content:
#
# fadc250 config file - EXAMPLE
#
# this file contains settings for
# fADC250 - JLAB VXS Flash ADC 12-bit 250 Msps 16 ch
#
# format:
# ~~~~~~~
# CRATE rocbcal1 <- ROC name, crate name, usually IP name
# FADC250_ALLSLOTS <- just keyword - all settings after this line will be implemented
# for all slots, till FADC250_SLOTS will be met
# FADC250_SLOTS 3 8 15 <- slot_numbers - in which next settings will be implemented
# till file ends or next FADC250_SLOTS will be met
#
# FADC250_F_REV 0x0216 <- firmware revision (0x0 Bits:7-0)
# FADC250_B_REV 0x0908 <- board revision (0x0 Bits:15-8)
# FADC250_ID 0xfadc <- board type (0x0 Bits:31-16)
#
# FADC250_MODE 1 <- process mode: 1-4 (0x10C Bits:2-0)
# FADC250_W_OFFSET 50 <- number of sample back from trigger point. (0x120)
# (in Manual it is PL=Trigger_Window(ns) * 250MHz)
# FADC250_W_WIDTH 49 <- number of ADC sample to include in trigger window. (0x11C)
# (in M: PTW=Trigger_Window(ns) * 250MHz, minimum is 6)
# FADC250_NSB 3 <- number of sample before trigger point to include in data processing. (0x124)
# This include the trigger Point. (minimum is 2 in all mode)
# FADC250_NSA 6 <- number of sample after trigger point to include in data processing. (0x128)
# Minimum is (6 in mode 2) and ( 3 in mode 0 and 1).
# Number of sample report is 1 more for odd and 2 more for even NSA number.
# FADC250_NPEAK 1 <- number of Pulses in Mode 2 and 3. (0x10C Bits:6-5)
#
# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - channels ##
# FADC250_ADC_MASK 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 <- channel enable mask (0x110)
# FADC250_TRG_MASK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- trigger enable mask
# (channel includes in global trigger, if bit set to 1)
# FADC250_TET 110 <- board Trigger Energy Threshold (TET), same for all 16 channels
# FADC250_CH_TET 0 110 <- channel# and TET_value for this channel
# FADC250_ALLCH_TET 111 222 2 3 4 5 6 7 8 9 10 11 12 13 14 15 <- 16 TETs (0x12C - 0x148)
#
# FADC250_DAC 3300 <- board DAC, one and the same for all 16 channels
# FADC250_CH_DAC 0 3300 <- channel# and DAC_value for this channel
# FADC250_ALLCH_DAC 3300 3280 3310 3280 3310 3280 3310 3280 3300 3280 3300 3280 3310 3280 3310 3280 <- 16 DACs
#
# FADC250_PED 210 <- board Pedestals, same for all channels
# FADC250_CH_PED 0 210 <- channel# and Pedestal_value for this channel
# FADC250_ALLCH_PED 210 220 210 215 215 220 220 210 210 215 215 220 220 210 215 220 <- 16 PEDs
CRATE rocfcal5
############################
FADC250_SLOTS 3
#########################
FADC250_ALLCH_DAC 3385 3399 3387 3396 3392 3396 3395 3374 3389 3401 3399 3391 3387 3381 3387 3393
############################
FADC250_SLOTS 4
#########################
FADC250_ALLCH_DAC 3355 3362 3350 3340 3364 3350 3359 3368 3359 3369 3386 3374 3377 3392 3352 3349
############################
FADC250_SLOTS 5
#########################
FADC250_ALLCH_DAC 3361 3378 3371 3367 3369 3380 3375 3376 3351 3380 3346 3372 3351 3371 3343 3381
############################
FADC250_SLOTS 6
#########################
FADC250_ALLCH_DAC 3367 3365 3356 3362 3361 3340 3347 3345 3363 3359 3349 3392 3360 3354 3355 3360
############################
FADC250_SLOTS 7
#########################
FADC250_ALLCH_DAC 3361 3351 3354 3362 3352 3373 3371 3344 3372 3381 3377 3341 3362 3382 3336 3350
############################
FADC250_SLOTS 8
#########################
FADC250_ALLCH_DAC 3345 3386 3362 3371 3346 3373 3388 3357 3376 3368 3359 3355 3369 3361 3365 3361
############################
FADC250_SLOTS 9
#########################
FADC250_ALLCH_DAC 3365 3337 3379 3354 3359 3373 3362 3386 3361 3386 3382 3373 3339 3377 3362 3342
############################
FADC250_SLOTS 10
#########################
FADC250_ALLCH_DAC 3357 3362 3353 3369 3378 3374 3379 3372 3357 3338 3359 3362 3357 3363 3352 3375
############################
FADC250_SLOTS 13
#########################
FADC250_ALLCH_DAC 3378 3386 3408 3374 3378 3369 3363 3349 3376 3376 3364 3352 3372 3358 3366 3371
############################
FADC250_SLOTS 14
#########################
FADC250_ALLCH_DAC 3373 3354 3369 3389 3388 3358 3365 3372 3344 3379 3393 3376 3365 3360 3372 3361
############################
FADC250_SLOTS 15
#########################
FADC250_ALLCH_DAC 3354 3354 3339 3341 3363 3368 3370 3367 3371 3376 3335 3347 3385 3351 3353 3379
############################
FADC250_SLOTS 16
#########################
FADC250_ALLCH_DAC 3378 3378 3360 3363 3368 3363 3356 3375 3338 3382 3359 3352 3388 3371 3381 3339
############################
FADC250_SLOTS 17
#########################
FADC250_ALLCH_DAC 3375 3358 3351 3385 3362 3372 3343 3377 3378 3369 3347 3352 3382 3362 3345 3341
############################
FADC250_SLOTS 18
#########################
FADC250_ALLCH_DAC 3352 3374 3358 3365 3376 3383 3359 3355 3376 3370 3368 3357 3355 3378 3352 3376
############################
FADC250_SLOTS 19
#########################
FADC250_ALLCH_DAC 3388 3372 3359 3347 3371 3368 3397 3358 3379 3372 3371 3382 3406 3365 3378 3382