Content:
#! Run type:: COSMIC Config:: TRG_COSMIC_BCAL_b40.conf
#! OUTPUT NAME:: /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/TRG_COSMIC_BCAL_b40.conf
#! (Re)Created:: on Sun Dec 3 08:47:00 EST 2017
#!
#! Run type:: PHYSICS_8 Config:: TRG_FCAL_BCAL_m8_b1bf1.conf
#! CONFIG FILE:: /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/TRG_FCAL_BCAL_m8_b1bf1.conf
#! (Re)Created:: on Wed Apr 29 12:06:51 EDT 2015
#!
# DSC2_WIDTH 20 40 <- TDC width (ns), TRG width (ns)
# DSC2_THRESHOLD 20 50 <- board threshold: TDC threshold (mV), TRG threshold (mV)
#
# TS_TRIG_TYPE 1 - Internal Pulser
# 2 - External FP
# 4 - GTP
# 6 - GTP + External
#
#
# TS_FP_INPUTS - List of enabled FP inputs
#
#
# TS_SOFT_TRIG
# Trigger type (type 1 or 2 for playback)
# Number of events to trigger
# Period multiplier (depends on range 0-0x7FFF)
# Range 1 - min 120ns, increments of 30ns up to 983.13u
# 2 - min 120ns, increments of 30.72us up to 1.007s
#
#
# TI_MASTER 1 - Stand alone with master TI
#
# TI_MASTER_TRIG 1 - soft, 2 - external pulser, 3 - playback
#
# TI_SOFT_TRIG
# Trigger type (type 1 or 2 for playback)
# Number of events to trigger
# Period multiplier (depends on range 0-0x7FFF)
# Range 1 - min 120ns, increments of 30ns up to 983.13u
# 2 - min 120ns, increments of 30.72us up to 1.007s
#
# F1TDC_CLOCK 0 <- Clock Source (0 = Internal 32 MHz)
# (1 = External 31.25 MHz)
# F1TDC_VERSION 2 <- Module Version (2 = High Resolution, synchronous, 32 channels)
# (3 = Normal Resolution, synchronous, 48 channels)
# set bin size from 0.056 to 0.058 -> Beni!
# F1TDC_BIN_SIZE 0.058 <- Bin size (ns)
# F1TDC_LATENCY 3000.0 <- Trigger latency (ns)
# F1TDC_WINDOW 1000.0 <- Trigger window (ns)
==========================
TRIGGER
==========================
#CALIBRATION 1
TS_TRIG_TYPE 4
TS_FP_INPUTS 3 9 10 12
#TS_FP_DELAY 9 24
#TS_FP_DELAY 10 50
#TS_FP_DELAY 9 27
#TS_FP_DELAY 10 53
#04/15/2016
TS_FP_DELAY 9 23
TS_FP_DELAY 10 44
TS_FP_DELAY 3 427
TS_SOFT_TRIG 1 0 0x1F 1
# TS_TD_SLOTS 3 4 5 6 7 8 14
# TS_TD_SLOTS 3 4 7 8 14
# TS_TD_SLOTS 3 4 7 8 9 10 14
TS_TD_SLOTS 5 7 6 8 3 14 4
# SSP SLOT FIBER_EN SUM_ENABLE
SSP_SLOT 8 0xFF 1
# SSP for ST
# SSP_SLOT 6 0x1 0
# TYPE DELAY INT_WIDTH ENABLE
TRIG_EQ PS 20 5 0
TRIG_EQ BCAL_E 20 20 1
TRIG_EQ BCAL_C 12 0 0
TRIG_EQ FCAL 0 10 0
TRIG_EQ ST 22 3 0
TRIG_EQ TOF 12 10 0
TRIG_EQ TAGH 96 0 0
# TYPE LATENCY WIDTH FCAL_E BCAL_E EN_THR NHIT LANE FCAL_EMIN FCAL_EMAX BCAL_EMIN BCAL_EMAX PATTERN
TRIG_TYPE BFCAL 480 5 0 1 10000 0 0
TRIG_TYPE ST 480 4 1300 1900 1100 1 -1
TS_GTP_PRES 6 1
TS_GTP_PRES 1 6
#TS_GTP_PRES 0 2
#TS_GTP_PRES 1 2
#TS_GTP_PRES 2 2
#TS_GTP_PRES 3 2
#TS_GTP_PRES 0 10
#TS_GTP_PRES 1 5
#TS_GTP_PRES 2 5
TRIG_DELAY 0
DAC_CALIB 0
TI_FIBER_LATENCY_OFFSET 0x98
TS_COIN_WIND 15
#TS_TRIG_HOLD 1 5 1
TS_TRIG_HOLD 1 10 0
TS_TRIG_HOLD 2 127 0
TS_TRIG_HOLD 3 2 1
TS_TRIG_HOLD 4 40 0
BLOCKLEVEL 40
BUFFERLEVEL 4
==========================
GLOBAL
==========================
F1TDC_BIN_SIZE 0.058
FADC250_BUSY 3
FADC125_BUSY 3
FADC250_FORMAT 2
FADC125_FORMAT 1
-------------------------------------------------------------------
# use file:: -rw-rw-r-- 1 hdops hdops 785 Feb 10 2017 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/FCAL.master
==========================
FCAL
==========================
FADC250_MODE 9
FADC250_W_OFFSET 805
FADC250_W_WIDTH 70
FADC250_NSB 1
FADC250_NSA 15
FADC250_NPEAK 3
FADC250_NSAT 2
FADC250_READ_THR 108
FADC250_TRIG_BL 100
FADC250_TRIG_THR 165
FADC250_TRIG_NSB 3
FADC250_TRIG_NSA 10
FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default
FADC250_COM_VER default
#FADC250_USER_DIR /gluex/Subsystems/FCAL/FCAL_Analysis/DAQ/config
#FADC250_USER_VER spring2015v2
#FADC250_USER_DIR /gluonfs1/gluex/CALIB/FCAL/fadc250/user/fall_2015
#FADC250_USER_VER ring2_hot_v2
FADC250_USER_DIR /gluonfs1/gluex/CALIB/FCAL/fadc250/user/spring_2017
FADC250_USER_VER ring2_hot_v2
-------------------------------------------------------------------
# use file:: -rw-rw-r-- 1 hdops hdops 812 Jan 27 2017 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/BCAL.master
==========================
BCAL
==========================
FADC250_MODE 9
FADC250_W_OFFSET 815
# Dalton 2017-01-27
FADC250_W_WIDTH 100
FADC250_NSB 1
FADC250_NSA 26
FADC250_NPEAK 1
FADC250_NSAT 2
FADC250_READ_THR 105
FADC250_TRIG_BL 100
FADC250_TRIG_THR 120
FADC250_TRIG_NSB 3
FADC250_TRIG_NSA 19
FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default
FADC250_COM_VER default
FADC250_USER_DIR /gluex/CALIB/ALL/user
FADC250_USER_VER
#CTP_BCAL_THR 56000
#CTP_THR 10
# F1 TDC
F1TDC_WINDOW 400.
F1TDC_LATENCY 3400.
F1TDC_CLOCK 1
# LE discriminator
DSC2_WIDTH 40 40
DSC2_THRESHOLD 35 50
DSC2_COM_DIR /gluex/CALIB/ALL/dsc/default
DSC2_COM_VER default
-------------------------------------------------------------------
# use file:: -rw-rw-r-- 1 hdops hdops 2137 Feb 2 2017 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/TOF.master
==========================
TOF
==========================
# change latency and width from 510/200 to 910/100
# and change NSB and NSA from 3/6 to 5/20
# btw. it is BENI
# changed NSB & NSA from 5/20 to 10/45 (eugenio)
FADC250_MODE 9
FADC250_W_OFFSET 800
FADC250_W_WIDTH 80
FADC250_NSB 1
FADC250_NSA 25
FADC250_NPEAK 3
FADC250_NSAT 2
FADC250_READ_THR 110
FADC250_TRIG_BL 100
FADC250_TRIG_THR 110
FADC250_TRIG_NSB 3
FADC250_TRIG_NSA 15
FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default
FADC250_COM_VER default
FADC250_USER_DIR /home/
FADC250_USER_VER
#CTP_BCAL_THR 56000
# LE discriminator
#DSC2_WIDTH 10 10
DSC2_WIDTH 20 40
DSC2_THRESHOLD -12 -12
#DSC2_COM_DIR /gluex/CALIB/ALL/dsc/default
#DSC2_COM_VER default
# CAEN 1290
#TDC1290_W_WIDTH 750
TDC1290_W_WIDTH 800
#TDC1290_W_OFFSET -1750
#TDC1290_W_OFFSET -3640
TDC1290_W_OFFSET -3660
TDC1290_W_EXTRA 25
TDC1290_W_REJECT 50
TDC1290_BLT_EVENTS 1
TDC1290_N_HITS 64
TDC1290_ALMOSTFULL 16384
TDC1290_OUT_PROG 2
TDC1290_A24_A32 2
TDC1290_SNGL_BLT 3
TDC1290_SST_RATE 0
TDC1290_BERR_FIFO 1
TDC1290_EDGE 2
# TDC1290_RC SLOT CHIP TAP1 TAP2 TAP3 TAP4
TDC1290_RC 3 0 5 1 4 3
TDC1290_RC 3 1 5 5 1 3
TDC1290_RC 3 2 7 2 7 4
TDC1290_RC 3 3 2 2 7 7
TDC1290_RC 4 0 0 1 6 3
TDC1290_RC 4 1 0 6 1 4
TDC1290_RC 4 2 3 2 0 3
TDC1290_RC 4 3 1 1 5 7
TDC1290_RC 5 0 6 0 1 6
TDC1290_RC 5 1 5 4 1 6
TDC1290_RC 5 2 2 1 2 3
TDC1290_RC 5 3 3 1 7 5
TDC1290_RC 6 0 1 4 6 6
TDC1290_RC 6 1 2 5 0 6
TDC1290_RC 6 2 7 0 7 5
TDC1290_RC 6 3 5 7 1 3
TDC1290_RC 7 0 3 1 6 6
TDC1290_RC 7 1 3 0 3 3
TDC1290_RC 7 2 7 4 1 3
TDC1290_RC 7 3 0 2 7 7
TDC1290_RC 8 0 7 7 0 4
TDC1290_RC 8 1 5 1 7 7
TDC1290_RC 8 2 3 0 4 2
TDC1290_RC 8 3 0 0 0 4
-------------------------------------------------------------------
# use file:: -rw-rw-r-- 1 hdops hdops 1010 Feb 2 2017 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/ST.master
==========================
ST
==========================
#change latency to 925 by BENI
# also change NSA and NSB from 3/6 to 5/20
FADC250_MODE 9
FADC250_W_OFFSET 819
FADC250_W_WIDTH 80
FADC250_NSB 5
FADC250_NSA 20
FADC250_NPEAK 3
FADC250_NSAT 2
# change FADC250_READ_THR from 800 -> 110 by pooser (5 mV)
# change FADC250_READ_THR from 110 -> 120 by pooser (10 mV)
FADC250_READ_THR 120
FADC250_TRIG_BL 100
FADC250_TRIG_THR 300
FADC250_TRIG_NSB 3
FADC250_TRIG_NSA 15
FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default
FADC250_COM_VER default
FADC250_USER_DIR /home/
FADC250_USER_VER
# F1 TDC
# change latency from 2100 to 3700
F1TDC_WINDOW 600.
F1TDC_LATENCY 3460.
F1TDC_CLOCK 1
# LE discriminator
# change DSC2_THRESHOLD from 100 -> 50 by pooser
DSC2_WIDTH 40 40
DSC2_THRESHOLD 50 60
#DSC2_COM_DIR /gluex/CALIB/ALL/dsc/default
#DSC2_COM_VER default
-------------------------------------------------------------------
# use file:: -rw-rw-r-- 1 hdops hdops 696 Feb 2 2017 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/TAGH.master
==========================
TAGH
==========================
FADC250_MODE 9
FADC250_W_OFFSET 895
FADC250_W_WIDTH 60
FADC250_NSB 3
FADC250_NSA 6
FADC250_NPEAK 3
FADC250_NSAT 2
# changed from 120 to 300
FADC250_READ_THR 300
FADC250_TRIG_BL 100
FADC250_TRIG_THR 200
FADC250_TRIG_NSB 3
FADC250_TRIG_NSA 6
FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default
FADC250_COM_VER default
FADC250_USER_DIR /home/
FADC250_USER_VER
CTP_USE 0
# F1 TDC
F1TDC_WINDOW 300.
F1TDC_LATENCY 3600.
F1TDC_CLOCK 1
# LE discriminator
DSC2_WIDTH 40 40
DSC2_THRESHOLD 45 45
-------------------------------------------------------------------
# use file:: -rw-rw-r-- 1 hdops hdops 1392 Feb 10 2017 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/TAGM.master
==========================
TAGM
==========================
FADC250_MODE 9
FADC250_W_OFFSET 890
FADC250_W_WIDTH 60
FADC250_NSB 3
FADC250_NSA 6
FADC250_NPEAK 3
FADC250_NSAT 2
# For low gain mode
#FADC250_READ_THR 115
# For high gain mode
#FADC250_READ_THR 180 (changed 3/30/2016 for high-gain running RTJ)
#FADC250_READ_THR 140
FADC250_READ_THR 115 # 2/4/17 by AEB, new fibers not yet calibrated
FADC250_TRIG_BL 100
FADC250_TRIG_THR 115 # (match read thr, 2/4/17 by AEB)
#FADC250_TRIG_THR 400 #(new defaults 4/21/16 by AEB)
FADC250_TRIG_NSB 3
FADC250_TRIG_NSA 15
FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default
FADC250_COM_VER default
FADC250_USER_DIR /home
FADC250_USER_VER
#FADC250_USER_DIR /gluex/Subsystems/TAGM/calib
#FADC250_USER_VER test_v1
CTP_USE 0
# F1 TDC
F1TDC_WINDOW 300.
F1TDC_LATENCY 3600.
F1TDC_CLOCK 1
# LE discriminator
# Change for high gain mode
DSC2_WIDTH 40 40
#DSC2_THRESHOLD 10 60
#DSC2_THRESHOLD 20 20
#DSC2_THRESHOLD 12 12 (changed 2/25/16 aebarnes)
#DSC2_THRESHOLD 100 150 (changed 3/30/2016 for high-gain running RTJ)
#DSC2_THRESHOLD 5 5 (changed for diamond alignment aebarnes 2/20/16)
DSC2_THRESHOLD 12 12 # 2/5/17 by AEB, new fiber calib not finished
-------------------------------------------------------------------
# use file:: -rw-rw-r-- 1 hdops hdops 502 Dec 17 2016 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/PS.master
==========================
PS
==========================
FADC250_MODE 9
FADC250_W_OFFSET 835
FADC250_W_WIDTH 100
FADC250_NSB 3
FADC250_NSA 10
FADC250_NPEAK 3
FADC250_READ_THR 130
FADC250_TRIG_BL 100
FADC250_TRIG_THR 200
FADC250_TRIG_NSB 3
FADC250_TRIG_NSA 15
FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default
FADC250_COM_VER default
FADC250_USER_DIR /home/somov/conf/cosmic
FADC250_USER_VER
-------------------------------------------------------------------
# use file:: -rw-rw-r-- 1 hdops hdops 500 Dec 17 2016 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/PSC.master
==========================
PSC
==========================
FADC250_MODE 9
FADC250_W_OFFSET 835
FADC250_W_WIDTH 100
FADC250_NSB 3
FADC250_NSA 6
FADC250_NPEAK 3
FADC250_READ_THR 150
FADC250_TRIG_BL 100
FADC250_TRIG_THR 150
FADC250_TRIG_NSB 3
FADC250_TRIG_NSA 6
# F1 TDC
F1TDC_WINDOW 600
F1TDC_LATENCY 3540
F1TDC_CLOCK 1
# LE discriminator
DSC2_WIDTH 40 40
DSC2_THRESHOLD 40 40
-------------------------------------------------------------------
# use file:: -rw-rw-r-- 1 hdops hdops 338 Feb 10 2017 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/TPOL.master
==========================
TPOL
==========================
FADC250_MODE 10
FADC250_W_OFFSET 795
FADC250_W_WIDTH 100
FADC250_NSB 3
FADC250_NSA 10
FADC250_NPEAK 1
FADC250_READ_THR 150
FADC250_TRIG_BL 100
FADC250_TRIG_THR 500
FADC250_TRIG_NSB 3
FADC250_TRIG_NSA 6
-------------------------------------------------------------------
# use file:: -rw-rw-r-- 1 hdops hdops 715 Jan 27 2017 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/CDC.master
==========================
CDC
==========================
# FADC125_MODE can be:
# 3 = CDC_short 6 = CDC_long
# 4 = FDC_short 7 = FDC_sum_long
# 5 = FDC_amp_short 8 = FDC_amp_long
FADC125_MODE 3
FADC125_W_OFFSET 438
FADC125_W_WIDTH 200
FADC125_IE 200
FADC125_NPEAK 1
FADC125_PG 4
FADC125_P1 4
FADC125_P2 4
FADC125_IBIT 4
FADC125_ABIT 3
FADC125_PBIT 0
FADC125_TH 60
FADC125_TL 15
FADC125_THR 500
FADC125_DAC 800
FADC125_COM_DIR /gluex/CALIB/ALL/fadc125/spring2017
FADC125_COM_VER default
FADC125_USER_DIR /gluex/
FADC125_USER_VER
-------------------------------------------------------------------
# use file:: -rw-rw-r-- 1 hdops hdops 1080 Feb 3 2017 /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/master_config/FDC.master
==========================
FDC
==========================
# FADC125_MODE can be:
# 3 = CDC_short 6 = CDC_long
# 4 = FDC_short 7 = FDC_sum_long
# 5 = FDC_amp_short 8 = FDC_amp_long
FADC125_MODE 5
FADC125_W_OFFSET 414
FADC125_W_WIDTH 80
FADC125_IE 16
FADC125_NPEAK 1
FADC125_PG 4
FADC125_P1 4
FADC125_P2 4
FADC125_IBIT 4
FADC125_ABIT 0
FADC125_PBIT 0
FADC125_TH 40
FADC125_TL 10
FADC125_THR 70
FADC125_DAC 800
FADC125_COM_DIR /gluex/CALIB/ALL/fadc125/spring2017
FADC125_COM_VER default
FADC125_USER_DIR /gluex/
FADC125_USER_VER
# F1 TDC
# change latency and window back to what we expect from ADCs (Beni)
F1TDC_WINDOW 600.
F1TDC_LATENCY 3360.
#F1TDC_BIN_SIZE 0.112
# High-resolution board in slot 17
# changed by Beni (loser) 2014.10.6
F1TDC_HR_WINDOW 1000.
F1TDC_HR_LATENCY 1160.
# set bin size from 0.056 to 0.058 -> Beni!
#F1TDC_HR_BIN_SIZE 0.058
F1TDC_CLOCK 1