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#! Run type:: PHYSICS_8 Config:: TRG_FCAL_BCAL_m8_b1bf1.conf
#! CONFIG FILE:: /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/TRG_FCAL_BCAL_m8_b1bf1.conf
#! (Re)Created:: on Wed Apr 29 12:06:51 EDT 2015
#!
# DSC2_WIDTH 20 40 <- TDC width (ns), TRG width (ns)
# DSC2_THRESHOLD 20 50 <- board threshold: TDC threshold (mV), TRG threshold (mV)
#
# TS_TRIG_TYPE 1 - Internal Pulser
# 2 - External FP
# 4 - GTP
# 6 - GTP + External
#
#
# TS_FP_INPUTS - List of enabled FP inputs
#
#
# TS_SOFT_TRIG
# Trigger type (type 1 or 2 for playback)
# Number of events to trigger
# Period multiplier (depends on range 0-0x7FFF)
# Range 1 - min 120ns, increments of 30ns up to 983.13u
# 2 - min 120ns, increments of 30.72us up to 1.007s
#
#
# TI_MASTER 1 - Stand alone with master TI
#
# TI_MASTER_TRIG 1 - soft, 2 - external pulser, 3 - playback
#
# TI_SOFT_TRIG
# Trigger type (type 1 or 2 for playback)
# Number of events to trigger
# Period multiplier (depends on range 0-0x7FFF)
# Range 1 - min 120ns, increments of 30ns up to 983.13u
# 2 - min 120ns, increments of 30.72us up to 1.007s
#
# F1TDC_CLOCK 0 <- Clock Source (0 = Internal 32 MHz)
# (1 = External 31.25 MHz)
# F1TDC_VERSION 2 <- Module Version (2 = High Resolution, synchronous, 32 channels)
# (3 = Normal Resolution, synchronous, 48 channels)
# set bin size from 0.056 to 0.058 -> Beni!
# F1TDC_BIN_SIZE 0.058 <- Bin size (ns)
# F1TDC_LATENCY 3000.0 <- Trigger latency (ns)
# F1TDC_WINDOW 1000.0 <- Trigger window (ns)
==========================
TRIGGER
==========================
#CALIBRATION 1
# TS_TRIG_TYPE 2
TS_TRIG_TYPE 1
TS_FP_INPUTS 3 9 10 12
#TS_FP_DELAY 9 24
#TS_FP_DELAY 10 50
#TS_FP_DELAY 9 27
#TS_FP_DELAY 10 53
#04/15/2016
TS_FP_DELAY 9 23
TS_FP_DELAY 10 44
TS_FP_DELAY 3 427
TS_SOFT_TRIG 1 65535 0x5F 1
TS_TD_SLOTS 4
# SSP SLOT FIBER_EN SUM_ENABLE
SSP_SLOT 8 0xFF 1
SSP_SLOT 9 0x3F 1
# TYPE DELAY INT_WIDTH ENABLE
# Spring 2017 initial
TRIG_EQ PS 35 10 0
TRIG_EQ BCAL_E 12 20 0
TRIG_EQ BCAL_C 20 0 0
TRIG_EQ FCAL 8 10 0
TRIG_EQ ST 31 3 0
TRIG_EQ TOF 20 10 0
# Change ST time to from 30 to 31 and TAGH delay from 105 to 106
TRIG_EQ TAGH 106 0 1
# TRIG_EQ BCAL_E 20 20 1
# TRIG_EQ FCAL 8 10 1
# TYPE LATENCY WIDTH FCAL_E BCAL_E EN_THR NHIT LANE FCAL_EMIN FCAL_EMAX BCAL_EMIN BCAL_EMAX PATTERN
TRIG_TYPE BFCAL 440 5 25 1 45000 0 -1 200 65535 0 65535
# TS_GTP_PRES 0 11
# TS_GTP_PRES 2 11
# TS_GTP_PRES 3 11
# TS_GTP_PRES 8 1
# TS_GTP_PRES 8 7
#TS_GTP_PRES 0 2
#TS_GTP_PRES 1 2
#TS_GTP_PRES 2 2
#TS_GTP_PRES 3 2
#TS_GTP_PRES 0 10
#TS_GTP_PRES 1 5
#TS_GTP_PRES 2 5
TRIG_DELAY 0
DAC_CALIB 0
TI_FIBER_LATENCY_OFFSET 0x98
TS_COIN_WIND 15
# TEST 2, THR = 3
TS_TRIG_HOLD 1 10 0
TS_TRIG_HOLD 2 127 0
TS_TRIG_HOLD 4 40 0
TS_TRIG_HOLD 3 2 1
# TS_SYNC_INT 1000
# 2/7/16 changed to 5000
TS_SYNC_INT 5000
TI_MASTER 0
TI_MASTER_TRIG 1
TI_FP_INPUTS 3
# TI_SOFT_TRIG 1 10000 0x7FFF 1
TI_SOFT_TRIG 1 65535 0x1F 1
BLOCKLEVEL 40
BUFFERLEVEL 4
# BLOCKLEVEL 1
# BUFFERLEVEL 1
==========================
GLOBAL
==========================
F1TDC_BIN_SIZE 0.058
FADC250_BUSY 3
FADC125_BUSY 3
FADC250_FORMAT 2
FADC125_FORMAT 1
==========================
DIRC
==========================
SSP_W_OFFSET 177
SSP_W_WIDTH 99
SSP_COM_DIR /gluex/CALIB/ALL/ssp/default
SSP_COM_VER default