Content:
#! Run type:: PHYSICS_8 Config:: TRG_FCAL_BCAL_m8_b1bf1.conf
#! CONFIG FILE:: /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/TRG_FCAL_BCAL_m8_b1bf1.conf
#! (Re)Created:: on Wed Apr 29 12:06:51 EDT 2015
#!
# DSC2_WIDTH 20 40 <- TDC width (ns), TRG width (ns)
# DSC2_THRESHOLD 20 50 <- board threshold: TDC threshold (mV), TRG threshold (mV)
#
# TS_TRIG_TYPE 1 - Internal Pulser
# 2 - External FP
# 4 - GTP
# 6 - GTP + External
#
#
# TS_FP_INPUTS - List of enabled FP inputs
#
#
# TS_SOFT_TRIG
# Trigger type (type 1 or 2 for playback)
# Number of events to trigger
# Period multiplier (depends on range 0-0x7FFF)
# Range 1 - min 120ns, increments of 30ns up to 983.13u
# 2 - min 120ns, increments of 30.72us up to 1.007s
#
#
# TI_MASTER 1 - Stand alone with master TI
#
# TI_MASTER_TRIG 1 - soft, 2 - external pulser, 3 - playback
#
# TI_SOFT_TRIG
# Trigger type (type 1 or 2 for playback)
# Number of events to trigger
# Period multiplier (depends on range 0-0x7FFF)
# Range 1 - min 120ns, increments of 30ns up to 983.13u
# 2 - min 120ns, increments of 30.72us up to 1.007s
#
# F1TDC_CLOCK 0 <- Clock Source (0 = Internal 32 MHz)
# (1 = External 31.25 MHz)
# F1TDC_VERSION 2 <- Module Version (2 = High Resolution, synchronous, 32 channels)
# (3 = Normal Resolution, synchronous, 48 channels)
# set bin size from 0.056 to 0.058 -> Beni!
# F1TDC_BIN_SIZE 0.058 <- Bin size (ns)
# F1TDC_LATENCY 3000.0 <- Trigger latency (ns)
# F1TDC_WINDOW 1000.0 <- Trigger window (ns)
==========================
TRIGGER
==========================
USE_PLAYBACK 0
TS_TRIG_TYPE 6
TS_FP_INPUTS 5
TS_FP_DELAY 5 417
TS_TD_SLOTS 3 14 15 9
# SSP SLOT FIBER_EN SUM_ENABLE
SSP_SLOT 14 0x1 1
# TYPE DELAY INT_WIDTH ENABLE
# Spring 2017 initial
TRIG_EQ PS 35 10 0
TRIG_EQ BCAL_E 12 20 0
TRIG_EQ BCAL_C 20 0 0
TRIG_EQ FCAL 8 10 0
TRIG_EQ ST 31 3 0
TRIG_EQ TOF 20 10 0
TRIG_EQ CCAL 4 15 1
# Change ST time to from 30 to 31 and TAGH delay from 105 to 106
TRIG_EQ TAGH 106 0 0
# TYPE LATENCY WIDTH FCAL_E BCAL_E EN_THR NHIT LANE FCAL_EMIN FCAL_EMAX BCAL_EMIN BCAL_EMAX PATTERN
TRIG_TYPE BFCAL 440 5 0 0 1000 0 0 0 65535 0 65535
# TRIG_TYPE BFCAL 440 5 0 0 8000 0 0 0 65535 0 65535
# TS_GTP_PRES 0 11
TRIG_DELAY 0
DAC_CALIB 0
TI_FIBER_LATENCY_OFFSET 0x98
TS_COIN_WIND 15
# TEST 2, THR = 3
TS_TRIG_HOLD 1 10 0
TS_TRIG_HOLD 2 127 0
TS_TRIG_HOLD 4 40 0
TS_TRIG_HOLD 3 2 1
# TS_SYNC_INT 1000
# 2/7/16 changed to 5000
TS_SYNC_INT 10000
BLOCKLEVEL 40
BUFFERLEVEL 4
==========================
GLOBAL
==========================
F1TDC_BIN_SIZE 0.058
FADC250_BUSY 3
FADC125_BUSY 3
FADC250_FORMAT 2
FADC125_FORMAT 1
==========================
CCAL
==========================
FADC250_MODE 9
FADC250_W_OFFSET 805
#FADC250_W_OFFSET 900
FADC250_W_WIDTH 100
FADC250_NSB 1
FADC250_NSA 15
FADC250_NPEAK 1
FADC250_NSAT 2
FADC250_READ_THR 108
# Use waveforrms for the TAC calibration
# FADC250_READ_THR 10
FADC250_TRIG_BL 100
FADC250_TRIG_THR 200
FADC250_TRIG_NSB 3
FADC250_TRIG_NSA 10
FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default
FADC250_COM_VER default
FADC250_USER_DIR /gluonfs1/gluex/CALIB/FCAL/fadc250/user/spring_2018
FADC250_USER_VER
==========================
TAGH
==========================
FADC250_MODE 9
#FADC250_W_OFFSET 895
FADC250_W_OFFSET 905
FADC250_W_WIDTH 100
FADC250_NSB 3
FADC250_NSA 6
FADC250_NPEAK 3
# changed from 120 to 300
FADC250_READ_THR 300
#FADC250_READ_THR 10
FADC250_TRIG_BL 100
FADC250_TRIG_THR 200
FADC250_TRIG_NSB 3
FADC250_TRIG_NSA 15
#FADC250_COM_DIR /home/somov/setups/tagh/parms/common/fadc250
#FADC250_COM_VER dac3200
FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default
FADC250_COM_VER default
FADC250_USER_DIR /home/
FADC250_USER_VER
CTP_USE 0
# F1 TDC
F1TDC_WINDOW 600.
F1TDC_LATENCY 3600.
F1TDC_CLOCK 1
# LE discriminator
DSC2_WIDTH 20 40
DSC2_THRESHOLD 45 45
==========================
TAGM
==========================
FADC250_MODE 9
FADC250_W_OFFSET 905
#changed from 100 to 60 (12/17/2016)
FADC250_W_WIDTH 100
FADC250_NSB 3
FADC250_NSA 6
FADC250_NPEAK 3
FADC250_NSAT 2
FADC250_READ_THR 150 # 1/14/18 by AEB/RTJ
FADC250_TRIG_BL 100
FADC250_TRIG_THR 150 # (match read thr, 1/14/18 by AEB/RTJ)
FADC250_TRIG_NSB 3
FADC250_TRIG_NSA 15
FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default
FADC250_COM_VER default
FADC250_USER_DIR /gluex/CALIB/TAGM/fadc250/user/spring_2018
FADC250_USER_VER fall_2018_v1
CTP_USE 0
# F1 TDC
F1TDC_WINDOW 600.
F1TDC_LATENCY 3600.
F1TDC_CLOCK 1
# LE discriminator
# Change for high gain mode
DSC2_WIDTH 20 40
DSC2_COM_DIR /gluex/CALIB/ALL/dsc/spring-2018
DSC2_COM_VER fall_2018_v1
==========================
TABS
==========================
FADC250_MODE 10
FADC250_W_OFFSET 805
FADC250_W_WIDTH 100
FADC250_NSB 3
FADC250_NSA 10
FADC250_NPEAK 3
FADC250_READ_THR 120
FADC250_TRIG_BL 100
# FADC250_TRIG_THR 120
# Production
# FADC250_TRIG_THR 350
# 4/11/2018
FADC250_TRIG_THR 300
FADC250_TRIG_NSB 3
# FADC250_TRIG_NSA 15
# 4/11/2018
FADC250_TRIG_NSA 9
FADC250_COM_DIR /gluex/CALIB/ALL/fadc250/default
FADC250_COM_VER tac
FADC250_USER_DIR
FADC250_USER_VER
# LE discriminator
DSC2_WIDTH 40 40
#DSC2_THRESHOLD 20 20
DSC2_THRESHOLD 40 40
# CAEN 1290
TDC1290_W_WIDTH 3000
TDC1290_W_OFFSET -3500
TDC1290_W_EXTRA 25
TDC1290_W_REJECT 50
TDC1290_BLT_EVENTS 1
TDC1290_N_HITS 64
TDC1290_ALMOSTFULL 16384
TDC1290_OUT_PROG 2
TDC1290_A24_A32 2
TDC1290_SNGL_BLT 3
TDC1290_SST_RATE 0
TDC1290_BERR_FIFO 1
TDC1290_EDGE 2