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#! Run type::  PHYSICS_8    Config::  TRG_FCAL_BCAL_m8_b1bf1.conf
#! CONFIG FILE:: /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/TRG_FCAL_BCAL_m8_b1bf1.conf
#! (Re)Created:: on  Wed Apr 29 12:06:51 EDT 2015
#!
#  DSC2_WIDTH      20  40     <- TDC width (ns),   TRG width (ns)
#  DSC2_THRESHOLD  20  50     <- board threshold:  TDC threshold (mV), TRG threshold (mV)
#
#  TS_TRIG_TYPE  1  -  Internal Pulser
#                2  -  External FP
#                4  -  GTP
#                6  -  GTP + External
#
#
#  TS_FP_INPUTS  - List of enabled  FP  inputs
#   
#
#  TS_SOFT_TRIG
#    Trigger type (type 1 or 2 for playback)
#    Number of events to trigger
#    Period multiplier (depends on range 0-0x7FFF)
#    Range 1  -   min  120ns, increments of 30ns up to 983.13u
#          2  -   min  120ns, increments of 30.72us up to 1.007s
#
#
#  TI_MASTER 1 - Stand alone with master TI
#
#  TI_MASTER_TRIG 1 - soft, 2 - external pulser, 3 - playback
#
#  TI_SOFT_TRIG
#    Trigger type (type 1 or 2 for playback)
#    Number of events to trigger
#    Period multiplier (depends on range 0-0x7FFF)
#    Range 1  -   min  120ns, increments of 30ns up to 983.13u
#          2  -   min  120ns, increments of 30.72us up to 1.007s
#
#  F1TDC_CLOCK     0       <- Clock Source (0 = Internal 32 MHz)
#                                       (1 = External 31.25 MHz)
#  F1TDC_VERSION   2       <- Module Version (2 = High Resolution, synchronous, 32 channels)
#                                         (3 = Normal Resolution, synchronous, 48 channels)
# set bin size from 0.056 to 0.058 -> Beni!
#  F1TDC_BIN_SIZE  0.058   <- Bin size (ns)
#  F1TDC_LATENCY   3000.0  <- Trigger latency (ns)
#  F1TDC_WINDOW    1000.0  <- Trigger window (ns)
#
#
#     DIRC configuration
#
#   3 SSP modules 
#     SSP     -  32 FIBERS
#     FIBER   -  3  ASICS
#     ASIC    -  1  DAC setting (threshold)
#                64 CHANNELS (64 GAINS)
# 
#  In the DIRC section, global parameters are set for all SSP modules
#
#  Individual GAINS and DAC values can be set (overwritten) in the file:
#          /gluex/CALIB/ALL/ssp/default/rocdirc_ssp_default.cnf
#
#
#  SSP_FIBER_W_WIDTH   Width and Position of the read out windoe
#  SSP_FIBER_W_OFFSET  
#
#  SSP_MAROC_REG_DAC0  DAC values for each ASIC (thresholds) 
#                               (range: 0 - 1023)
#
#  SSP_MAROC_REG_GAIN_0_15   Value  
#     Gains for channels 0 - 15
#     Gain range: 0 - 4    (Value range: 0 - 255,  64 corresponds to gain = 1)
#   
#
#  Enable Charge Injection (Test mode)
#
#   SSP_CTEST_ENABLE       1 - enable,  0 - disable
#   SSP_CTEST_DAC          Charge amplitude
#   SSP_PULSER             Pulser frequency
#   SSP_MAROC_REG_CTEST    Mask of enabled channels    
#
#

==========================
        TRIGGER
==========================

#CALIBRATION   1

TS_TRIG_TYPE  1

TS_FP_INPUTS  15

TS_FP_DELAY   15  417


TS_SOFT_TRIG  1  65535   0x5F  1

TS_TD_SLOTS  4  

# SSP      SLOT      FIBER_EN    SUM_ENABLE
SSP_SLOT     8         0xFF        1
SSP_SLOT     9         0x3F        1


#            TYPE       DELAY     INT_WIDTH     ENABLE
# Spring 2017 initial 

TRIG_EQ      PS          35         10           0
TRIG_EQ      BCAL_E      12         20           0
TRIG_EQ      BCAL_C      20          0           0
TRIG_EQ      FCAL        8          10           0
TRIG_EQ      ST          31          3           0
TRIG_EQ      TOF         20         10           0

# Change ST time to from 30 to 31 and TAGH delay from 105 to 106 
TRIG_EQ      TAGH        106         0           0

#            TYPE      LATENCY     WIDTH     FCAL_E    BCAL_E     EN_THR   NHIT LANE    FCAL_EMIN   FCAL_EMAX  BCAL_EMIN   BCAL_EMAX   PATTERN


TRIG_TYPE     BFCAL       440        5        25          1        45000    0     -1         200         65535       0        65535

#TS_GTP_PRES  0  10

TRIG_DELAY  0
DAC_CALIB   0 

TI_FIBER_LATENCY_OFFSET  0x98

TS_COIN_WIND  15

# TEST 2, THR = 3
TS_TRIG_HOLD  1  10    0
TS_TRIG_HOLD  2  127   0
TS_TRIG_HOLD  4  40    0
TS_TRIG_HOLD  3  2     1


TS_SYNC_INT  5000

TI_MASTER  0


BLOCKLEVEL   40
BUFFERLEVEL  4

#BLOCKLEVEL   1
#BUFFERLEVEL  1

==========================
        GLOBAL  
==========================

F1TDC_BIN_SIZE   0.058

FADC250_BUSY 3

FADC125_BUSY 3

FADC250_FORMAT  2

FADC125_FORMAT  1


==========================
         TOF   
==========================
FADC250_MODE         10
FADC250_W_OFFSET     800

FADC250_W_WIDTH      80
FADC250_NSB          1
FADC250_NSA          10
FADC250_NPEAK        3

FADC250_NSAT         2

FADC250_READ_THR     110

FADC250_TRIG_BL      100
FADC250_TRIG_THR     130 
FADC250_TRIG_NSB     3
FADC250_TRIG_NSA     15

FADC250_COM_DIR      /gluex/CALIB/ALL/fadc250/default
FADC250_COM_VER      default

FADC250_USER_DIR    /home/
FADC250_USER_VER    

#  LE discriminator

DSC2_WIDTH        20   40 
# Default
DSC2_THRESHOLD   -12  -12
DSC2_COM_DIR      /gluex/CALIB/ALL/dsc/default
DSC2_COM_VER      default


#  CAEN 1290

TDC1290_W_WIDTH    800
TDC1290_W_OFFSET -3660
TDC1290_W_EXTRA    25
TDC1290_W_REJECT   50


TDC1290_BLT_EVENTS 1
TDC1290_N_HITS     64
TDC1290_ALMOSTFULL 16384
TDC1290_OUT_PROG   2

TDC1290_A24_A32    2
TDC1290_SNGL_BLT   3
TDC1290_SST_RATE   0
TDC1290_BERR_FIFO  1

TDC1290_EDGE       2

TDC1290_INL        1

# TDC1290_RC  SLOT  CHIP  TAP1  TAP2  TAP3  TAP4

 TDC1290_RC  3   0   5   1   4   3
 TDC1290_RC  3   1   5   5   1   3
 TDC1290_RC  3   2   7   2   7   4
 TDC1290_RC  3   3   2   2   7   7
 TDC1290_RC  4   0   0   1   6   3
 TDC1290_RC  4   1   0   6   1   4
 TDC1290_RC  4   2   3   2   0   3
 TDC1290_RC  4   3   1   1   5   7
 TDC1290_RC  5   0   6   0   1   6
 TDC1290_RC  5   1   5   4   1   6
 TDC1290_RC  5   2   2   1   2   3
 TDC1290_RC  5   3   3   1   7   5
 TDC1290_RC  6   0   1   4   6   6
 TDC1290_RC  6   1   2   5   0   6
 TDC1290_RC  6   2   7   0   7   5
 TDC1290_RC  6   3   5   7   1   3
 TDC1290_RC  7   0   3   1   6   6
 TDC1290_RC  7   1   3   0   3   3
 TDC1290_RC  7   2   7   4   1   3
 TDC1290_RC  7   3   0   2   7   7
 TDC1290_RC  8   0   7   7   0   4
 TDC1290_RC  8   1   5   1   7   7
 TDC1290_RC  8   2   3   0   4   2
 TDC1290_RC  8   3   0   0   0   4




==========================
         DIRC  
==========================

SSP_FIBER_W_WIDTH   1000
SSP_FIBER_W_OFFSET  3400

SSP_REG_GLOBAL0       0x69306B87
SSP_REG_GLOBAL1       0x0

SSP_MAROC_REG_DAC0    400
SSP_MAROC_REG_DAC1    0

SSP_MAROC_REG_GAIN_0_15         64  64  64  64  64  64  64  64  64  64  64  64  64  64  64  64
SSP_MAROC_REG_GAIN_16_31        64  64  64  64  64  64  64  64  64  64  64  64  64  64  64  64
SSP_MAROC_REG_GAIN_32_47        64  64  64  64  64  64  64  64  64  64  64  64  64  64  64  64
SSP_MAROC_REG_GAIN_48_63        64  64  64  64  64  64  64  64  64  64  64  64  64  64  64  64

SSP_MAROC_REG_SUM         0x00000000    0x00000000
SSP_MAROC_REG_MASKOR      0x00000000    0x00000000

SSP_TDC_ENABLE        0xFFFFFFFF  0xFFFFFFFF  0xFFFFFFFF  0xFFFFFFFF  0xFFFFFFFF  0xFFFFFFFF

# Charge injection
# SSP_CTEST_ENABLE          0
# SSP_CTEST_DAC             1000
# SSP_PULSER                1000000

# SSP_MAROC_REG_CTEST       0x00000000    0x00000000


# Charge injection
SSP_CTEST_ENABLE          1
SSP_CTEST_DAC             1000
SSP_PULSER                5000

SSP_MAROC_REG_CTEST       0x11111111    0x11111111


SSP_COM_DIR      /gluex/CALIB/ALL/ssp/default
SSP_COM_VER      unitygain


# Configuration of the Reference SiPM
#          FADC settings
FADC250_MODE         9
FADC250_W_OFFSET     805

FADC250_W_WIDTH      100
FADC250_READ_THR     130

FADC250_TRIG_THR     110 

DSC2_THRESHOLD       20   20