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c#! Run type:: PHYSICS_8 Config:: TRG_FCAL_BCAL_m8_b1bf1.conf
#! CONFIG FILE:: /home/hdops/CDAQ/daq_dev_v0.31/daq/config/hd_all/TRG_FCAL_BCAL_m8_b1bf1.conf
#! (Re)Created:: on Wed Apr 29 12:06:51 EDT 2015
#!
# DSC2_WIDTH 20 40 <- TDC width (ns), TRG width (ns)
# DSC2_THRESHOLD 20 50 <- board threshold: TDC threshold (mV), TRG threshold (mV)
#
# TS_TRIG_TYPE 1 - Internal Pulser
# 2 - External FP
# 4 - GTP
# 6 - GTP + External
#
#
# TS_FP_INPUTS - List of enabled FP inputs
#
#
# TS_SOFT_TRIG
# Trigger type (type 1 or 2 for playback)
# Number of events to trigger
# Period multiplier (depends on range 0-0x7FFF)
# Range 1 - min 120ns, increments of 30ns up to 983.13u
# 2 - min 120ns, increments of 30.72us up to 1.007s
#
#
# TI_MASTER 1 - Stand alone with master TI
#
# TI_MASTER_TRIG 1 - soft, 2 - external pulser, 3 - playback
#
# TI_SOFT_TRIG
# Trigger type (type 1 or 2 for playback)
# Number of events to trigger
# Period multiplier (depends on range 0-0x7FFF)
# Range 1 - min 120ns, increments of 30ns up to 983.13u
# 2 - min 120ns, increments of 30.72us up to 1.007s
#
# F1TDC_CLOCK 0 <- Clock Source (0 = Internal 32 MHz)
# (1 = External 31.25 MHz)
# F1TDC_VERSION 2 <- Module Version (2 = High Resolution, synchronous, 32 channels)
# (3 = Normal Resolution, synchronous, 48 channels)
# set bin size from 0.056 to 0.058 -> Beni!
# F1TDC_BIN_SIZE 0.058 <- Bin size (ns)
# F1TDC_LATENCY 3000.0 <- Trigger latency (ns)
# F1TDC_WINDOW 1000.0 <- Trigger window (ns)
==========================
TRIGGER
==========================
#CALIBRATION 1
USE_PLAYBACK 0
TS_TRIG_TYPE 2
TS_FP_INPUTS 1
#TS_FP_DELAY 9 24
#TS_FP_DELAY 10 50
#TS_FP_DELAY 9 27
#TS_FP_DELAY 10 53
#04/15/2016
TS_FP_DELAY 9 23
TS_FP_DELAY 10 44
TS_FP_DELAY 3 427
TS_SOFT_TRIG 1 0 0xFF 1
TS_TD_SLOTS 4 14
# SSP SLOT FIBER_EN SUM_ENABLE
# SSP_SLOT 8 0xFF 1
# SSP_SLOT 9 0x3F 1
# SSP_SLOT 10 0x3F 1
# TYPE DELAY INT_WIDTH ENABLE
TRIG_EQ PS 20 5 1
TRIG_EQ BCAL_E 7 20 1
TRIG_EQ BCAL_C 12 0 0
TRIG_EQ FCAL 0 10 1
TRIG_EQ ST 22 3 1
TRIG_EQ TOF 12 10 0
TRIG_EQ TAGH 96 0 1
#TRIG_EQ PS 35 10 1
#TRIG_EQ BCAL_E 15 20 1
#TRIG_EQ BCAL_C 20 0 0
#TRIG_EQ FCAL 8 10 1
#TRIG_EQ ST 30 10 1
#TRIG_EQ TOF 20 10 0
# TRIG_EQ BCAL_E 20 20 1
# TRIG_EQ FCAL 8 10 1
# TYPE LATENCY WIDTH FCAL_E BCAL_E EN_THR NHIT LANE FCAL_EMIN FCAL_EMAX BCAL_EMIN BCAL_EMAX PATTERN
TRIG_TYPE BFCAL 480 5 10 2 18000 0 0 200 65535 0 65535
TRIG_TYPE BFCAL 480 5 0 1 25000 0 2
# Changed 03/31/16
#TRIG_TYPE BFCAL 440 5 0 1 18000 0 2
TRIG_TYPE PS 480 5 1300 1900 1100 0 3
TRIG_TYPE BFCAL 480 5 20 1 36000 0 5 200 65535 0 65535
TRIG_TYPE BFCAL 480 5 1 0 900 0 6
TRIG_TYPE ST 480 5 1300 1900 1100 1 6
TRIG_TYPE BCAL_COS 480 40 1500 2100 1300 0 -1
TRIG_TYPE TAGH 480 4 1 1 1100 1 1 0 65535 0 65535 0xF000
TRIG_TYPE ST 480 4 1300 1900 1100 1 1
TS_GTP_PRES 6 1
TS_GTP_PRES 1 6
#TS_GTP_PRES 0 2
#TS_GTP_PRES 1 2
#TS_GTP_PRES 2 2
#TS_GTP_PRES 3 2
#TS_GTP_PRES 0 10
#TS_GTP_PRES 1 5
#TS_GTP_PRES 2 5
TRIG_DELAY 0
DAC_CALIB 0
TI_FIBER_LATENCY_OFFSET 0x98
TS_COIN_WIND 15
# TS_TRIG_HOLD 63 0
# TS_TRIG_HOLD 62 1
TS_TRIG_HOLD 1 10 0
TS_TRIG_HOLD 4 40 0
# TS_SYNC_INT 1000
# 2/7/16 changed to 5000
# TS_SYNC_INT 5000
TI_MASTER 0
TI_MASTER_TRIG 1
# TI_FP_INPUTS 3
# TI_SOFT_TRIG 1 10000 0x7FFF 1
TI_SOFT_TRIG 1 10000 0x600 1
BLOCKLEVEL 20
BUFFERLEVEL 4
==========================
GLOBAL
==========================
F1TDC_BIN_SIZE 0.058
==========================
CDC
==========================
# CDC_short 3
# CDC_long 6
# FDC_short 4
# FDC_amp_short 5
# FDC_sum_long 7
# FDC_amp_long 8
FADC125_MODE 3
FADC125_W_OFFSET 455
FADC125_W_WIDTH 200
FADC125_IE 200
FADC125_NPEAK 1
FADC125_PG 4
FADC125_P1 4
FADC125_P2 4
FADC125_IBIT 4
FADC125_ABIT 3
FADC125_PBIT 0
FADC125_TH 90
FADC125_TL 25
FADC125_THR 500
FADC125_DAC 800
FADC125_COM_DIR /gluex/CALIB/ALL/fadc125/default/test
FADC125_COM_VER test
FADC125_USER_DIR /gluex/
FADC125_USER_VER
==========================
FDC
==========================
# CDC_short 3
# CDC_long 6
# FDC_short 4
# FDC_amp_short 5
# FDC_sum_long 7
# FDC_amp_long 8
FADC125_MODE 5
FADC125_W_OFFSET 455
FADC125_W_WIDTH 100
FADC125_IE 16
FADC125_NPEAK 1
FADC125_PG 4
FADC125_P1 4
FADC125_P2 4
FADC125_IBIT 4
FADC125_ABIT 0
FADC125_PBIT 0
FADC125_TH 40
FADC125_TL 10
FADC125_THR 70
FADC125_DAC 800
FADC125_COM_DIR /gluex/CALIB/ALL/fadc125/default
FADC125_COM_VER default
FADC125_USER_DIR /gluex/
FADC125_USER_VER
# F1 TDC
# change latency and window back to what we expect from ADCs (Beni)
F1TDC_WINDOW 1400.
F1TDC_LATENCY 3680.
#F1TDC_BIN_SIZE 0.112
# High-resolution board in slot 17
# changed by Beni (loser) 2014.10.6
F1TDC_HR_WINDOW 1000.
F1TDC_HR_LATENCY 1280.
# set bin size from 0.056 to 0.058 -> Beni!
#F1TDC_HR_BIN_SIZE 0.058
F1TDC_CLOCK 1