FADC Data Format Feb 25, 2014

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Location and Time

Room: CC F326-327

Time: 1:30pm-2:30pm

Remote Connection

ESNet: 8542553

(if problems, call phone in conference room: 757-269-6460)

Agenda

Minutes

Attendees: Naomi J., Beni Z., Lubomir P., David L.(chair), Elton S.

  • Naomi has implemented in software the FADC250 timing algorithm.
    • This was actually shown at the collaboration meeting, but since Curtis was presenting for her and it was put in last minute, we did not appreciate that this was what was being shown. (This is on slide 5 labeled "Tmax/2")
    • The FADC250 algorithm is simpler than previously thought. It identifies a peak and then looks for the point where the signal exceeds the half-peak height.
    • The plots indicate about a 20% worse resolution for the FADC250 algorithm than for Naomi's upsampling algorithm (130μm vs. 109μm)
  • Dave relayed a discussion he had with Fernando regarding the schedule for FADC125 firmware development
    • Fernando thought it would take roughly the same amount of effort to port the FADC250 code as to develop new code, but he would discuss this with Cody
    • After some discussion on this, the group agreed that if it really was no more effort, then we should try implement the new data format
    • We also decided that if the up sampling timing algorithm could not be cleanly implemented by the end of June, we would need to revert to using the FADC250 algorithm in order to guarantee something was available well in advance of the Oct. run.
    • The FADC125 document would need to be updated with the complete specification by the end of the week since Cody will begin work on this next week.

Addendum: After speaking with Cody, Fernando and he agreed that implementing the FADC250 data format would likely be quicker and therefore less risky schedule-wise than implementing a new data format. They will work on this first with the modification that they will try and include Naomi's timing algorithm.

  • We then discussed briefly the configuration parameters (i.e. registers) we'd like to have available on the FADC125
    • Pulse integral scaling factor. This can be an integer indicating power of 2 since that will just be a bit shift op in the algorithm.
    • Sparsification thresholds for each channel. It was though that having these might give an additional degree of flexibility. It was noted that we do have individual channel control for the DAC setting which gives similar functionality. If individual channel thresholds is problematic for some reason, we can revisit this.
    • Time offset
    • Naomi has a preliminary list on her CDC algorithm page.

Action Items:

  1. Send timing VHDL module and documentation to Cody (Naomi)
  2. Verify the # of bits required for the CDC integral (Naomi)
  3. Propose bit assignments for CDC data format (Naomi)
  4. Add section on timing algorithm to FADC125 document (Naomi)
  5. Add section on registers to FADC125 document (David)
  6. Send URL of document via e-mail (David)
  7. Add Lubomir's command data format to FADC125 document (David)