June 17, 2010 FDC meeting
- Cathode redesign: finalizing, card grounding (Roger, Fernando)
- Full-scale prototype tests
- tests with fADC FDC Log Book, pages 486 - 489 (Lubomir)
- cosmic tests (Beni)
Participants: Simon, Beni, Eugene, Casey, Roger, Mark, Fernando, Lubomir, and Gerard on the phone.
- The PR for the clean room was submitted at the end of last week. The specifications and estimate are linked above. The estimate is for $250K for the clean room, including the electrical installations, excluding the AC. According to the schedule, the installation must be completed and the room commissioned on Sep. 13 this year. The CC will take care of the network, including wireless. We will buy a color laser printer/copier/scanner for ~$700, i.e. low quality.
- We discussed the place to start setting up the wire stringing before going off-site. The two options: F117 and 126 in the EEL building. Fernando is concerned there will be no space in F117, wire stringing will take 2/3 of the space there. He will prepare a floor plan for F117 for the PCB testing. Casey and others emptied a table in F117. Mark had an idea to use two such tables and the thick aluminum plate (used now for vacuuming) for the wire stringing. F117 is cleaner than 126, but we discussed if we need a clean space, since we just want to try the stringing procedure, not to make real chambers. We want to build a new design one layer prototype, but this probably can't be done in F117. Lubomir was concerned that if there's a delay moving off-site we will have to build the prototype again in 126. We will discuss this on the next meeting also when Bill is back.
- fADC125: Gerard is working with Bryan Moffit and wants to repeat the rate test that Bryan did with his code. Fernando suggested not to discuss this at this meeting. High signal cutoff problem: in the distribution of the maximum wire signal (page 486, FDC logbook) we see a cutoff at about 11000 fADC units (~270mV), more pronounced at higher sense wire voltages (>2225V). The fADC cutoff and, approximately, the pre-amp saturation are at 2^14 = ~16000 and it is visible for both top and bottom strips. Fernando will investigate the wire board, since it is suppose to saturate at the same (>400mV) voltage as the cathode boards. Also we expect to see a peak (as Gerard noted) at the cutoff region, because the signals that saturates will have similar maximal values. There's no obvious peak there even at 2275V. Gerard said there's smearing by a up to 20% because of the sampling and suggested to use quadratic interpolation to find the maximum. Lubomir will do it.
- While Gerard was on the phone, Lubomir presented the results of the fADC tests. During the last (almost) week, the fADC125 was powered continuously, the temperature on the board was ~53degC always and there were no problems with the operation. The plateau, gain and strip resolution vs HV were studied (page 487 in FDC logbook) in order to choose the operational HV. Using lower threshold (~5mV at the fADC input) moves the beginning of the plateau down to ~2000-2050V (field voltage at 500V). However, the strip resolution get worse if lowering the HV. The resolution levels out above ~2225V, so probably ~2225V will be the operational HV. At this voltage some good fraction of the signals most likely saturates. Gerard asked if we are going do particle ID using dE/dX in which case probably we need even lower amplification. Beni and Simon explained that at the forward region the particles are minimum ionizing, so the signals will be similar the these with cosmics. Lubomir is concerned that now the cathode pre-amp cards are at their lowest possible setting (2.6mV/fC) for the high gain region. Fernando will look what modifications can be done so that we can lower the amplification with small steps if needed.
- Roger is working on the Bill's modifications: ready with one side of the foil and finishing the other. Additional grounding for the rigid-flex that was discussed on the last meeting: the cuts needed in the g10 cathode ring were designed by Bill, but he didn't send Roger the sizes. Roger discussed also some details of the foil flaps, to have copper or not in the cutout region. In any case we have to wait for Bill to finalize the cathode design.
Full-scale prototype test results
- Lubomir already presented some of the results from the tests with fADC. A good fraction of the chamber was scanned with the three cards connected to the fADC. More results will be presented at the next meeting.
- After the fADC tests, Beni connected the cards to the middle layer using the standard set-up (conventional ADCs for the strips, discriminators and TDCs for the wires). Beni had problems with the conditioning of the middle layer. For now he was able to work at the nominal HV of 2225V only at one sector. He will try changing the polarity to condition the chamber. Beni showed (logbook page 485) a plot with the ratio of the top to bottom strip sum; the result is similar to the one shown by Lubomir on the previous meeting using fADC: the signals on the top strips are bigger than on the bottom and this varies along the chamber by up to 20-30%. For now we explain it by shifts of the wires closer to the top cathode.
- We discussed ones more (now with Eugene) the space at F117. Lubomir asked if anybody else (except Fernando) wants to use F117 during this time. Eugene suggested to discuss this at the Hall D meeting on Monday. Eugene thinks that in any case there's no space in F117 to make the new design prototype, so we have to start setting up the wire stringing at 126.