Minutes 7-11-2007

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FDC Weekly Meeting

Date: July 11, 2007

Participants: Daniel, Simon, Brian, Kim, Tim, Chuck, Fernando, Joe

Next Meeting: July 18, 2007

Cathode Updates

 - Brian has not yet heard back from Sierra regarding whether or not
   they can make our cathode planes.  We are now assuming that they
   will say no.  Brian will move to contact CCT Marketing to give them
   the go ahead on the $14k tooling costs and have them make our
   boards for the small-scale prototype with 2-um copper on 1-mil Kapton
   backing.  We felt this was important to complete so that these boards
   are ready for testing in the B-field test coming up next month.


 - Calculations provided by Tim modeling the 
   loaded wire frame with a single (central) wire carrying the full 
   force load, indicated that the shearing force on the end of the
   frame would lead to failure.  He determined that we would be far
   from any failure point if the composite was made with high density
   Rohacell instead of low-density Rohacell.
 - Brian will check these calculations with a potentially destructive
   test of his existing composite wire frame.  He has already ordered
   the necessary high density Rohacell foam and will make another
   composite wire frame when this arrives.  This new version will have
   the nominal wire frame dimensions that is 5-mm thick overall.
 - We also decided that we should move to replace the CH2 spacers with
   this same composite design.  These frames will be much easier to
   handle than the CH2.
 - Brian's main worry is that the o-ring groove will fail.  That is to
   say, the spacer needs to have an o-ring groove machined into it on
   one side.  The depth of this groove is more than the 1/32-in thickness
   of the G10.  The plan was to machine in this groove and then to seal
   it with epoxy.  Brian's worry is that any flexing of the frame could
   cause the seal to crack.  He will test this on a prototype frame

Cathode Boards

 - Even though we have not reached a final decision with regard to
   backing or no-backing of the cathode boards, we all feel that the
   evidence and test results are indicating that a non-backed cathode
   simply cannot meet our flatness specifications in the environment
   inside the magnet.  We have discussed a number of options for including
   a backing structure that still aims to reduce the thickness in the
   active area.  To this end, Brian has ordered some 2-mm thick low
   density Rohacell that we will use as the backing in our next cathode

Magnetic Field Tests

 - DSC has finalized a loan agreement with IUCF to borrow 8 drift
   chambers to be used to define the external track through the magnet
   and the small-scale prototype.  These horizontal drift chambers 
   have a half-gap of roughly 5 mm and an area of roughly 45 x 25 cm**2.
   They should arrive at JLab before the end of next week.  DSC and
   Simon will work out a plan to recondition these chambers which have
   not been used in about 15 years.  In fact DSC built these chambers at
   IUCF for his thesis experiment!  Once calibrated, these chambers
   should provide a measurement of the track at the location of the
   small-scale prototype of roughly 200 um.
 - Simon will work with DSC to come up with a list of components that
   we need for the test and then work to dig up any missing cables.
   We will also finalize the test plan for the measurements.
 - Simon will do some measurements in Hall B to find out exactly what
   the space requirements are.  We would like to put 4 chambers and one
   trigger scintillator above the magnet and an identical set of chambers
   and trigger scintillator below the magnet.  The upper set should
   sit on a plastic sheet and the lower set should be raised off the
   floor.  All cabling, power lines, and gas lines should be strung so
   that they are not a trip hazard and do not get in the way of anyone
   wanting access to the downstream alcove and F.C..
 - Simon will start to prepare the electronics in the Test Lab for
   movement to Hall B.  He will also coordinate with Doug Tilles for
   the move.

Circuit Boards

 - Chuck and Kim will prepare list of detailed questions that they need
   to get answered to finalize the design of the STBs and HVTBs.  These
   lists should be ready for our next FDC meeting.

ASIC Developments

 - The first ASICs have arrived at UPenn where Mitch Newcomer is testing
   them.  We would like to be able to use these amplifiers to read out
   the small-scale prototype.  However there are compatibility issues
   with the chamber and the readout electronics.  To address the issues
   with the chamber, a small circuit board needs to be designed by
   Fernando to act as a go between for the daughter board and the chamber.
   On the read out side, the daughter boards will not be compatible with
   Gerard's shaper board, nor are they compatible with the VPI postamp.
   Fernando will think about what needs to be done and the priorities
   for this work.  We will discuss this more at the next FDC meeting.

Space Requirements

 - We had a discussion on the short term and longer term space needs for
   the FDC, both in the EEL building and the new planned test lab
   building (which should be on-line in roughly 2011).  The final ideas
   where handed over to Tim to present at the upcoming "new building
   discussion meeting".


 - Joe provided numbers (actually several weeks ago) on the modified
   readout cables that we are planning to use.  DSC and Simon need to
   meet with Dave Lawrence to get this modeled in the simulation.


 - Our requests for Monte Carlo simulations to address the question on
   the material in the active and in-active portions of the FDC still
   have not led to anything that we can use.  Simon and DSC will meet
   with Dave Lawrence to find out where the simulations are now and
   what needs to be done so that we can finalize the material designs.
   We have been waiting for answers for far too long and this has
   really hampered our ability to move the design forward.
 - We again discussed the need for simulation results to enable us to
   make a decision on the wire plane orientations within an FDC package.
   The nominal design is U,U,V,V,W,W and we are proposing something more
   like U,U',V,V',W,W' where the primed notation includes a half-cell
   offset in the wires between neighboring planes.  We need to find a
   way to address this issue.  It is already becoming clear that our
   tracking algorithms will require local left/right ambiguity resolution.

Work List

 - The FDC short-term work list has been posted on the FDC web site
   (see http://www.jlab.org/Hall-D/detector/fdc/).  This is continually
   being updated and DSC welcomes any feedback or comments from the group.

Minutes prepared by Daniel. Send any comments or corrections along.