Difference between revisions of "Bill's to do list"

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(2020 Summer DIRC To-do List)
 
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==2018==
 
# Priority list:
 
# Priority list:
#* Laser alignment and generating mis-alignment table
+
#* Laser alignment and generating mis-alignment table (Bill, Andrew). <span>&#10003;</span>
#* Feedthrough opening angle measurement and fish tank.
+
#* Feedthrough opening angle measurement and fish tank (Bill, Fernando). <span>&#10003;</span>
#* Light monitors testing and mounting
+
#* Light monitors testing and mounting (Bill, Keith). <span>&#10003;</span>
#* DIRC module cabling strategy.
+
#* DIRC module cabling strategy (Bill/Andrew). <span>&#10003;</span>
#* Hole opening on the backplate.
+
#* Hole opening on the backplate (Keith). <span>&#10003;</span>
#* Hole opening on the of the PMT mounting plate.
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#* Hole opening on the of the PMT mounting plate (Tim, Keith, Bobby). <span>&#10003;</span>
#* Plastic bolts and screws for the FPGA board.
+
#* Plastic bolts and screws for the FPGA board. (Chris) <span>&#10003;</span>
#* Recover PMT #9 and 10 and perform test.
+
#* Recover PMT #9 and 10 and perform test <span>&#10003;</span>
#* Spare micro-BNC cable for the big box.
+
#* Spare micro-BNC cable for the big box. (Omen) <span>&#10003;</span>
#* Cleaning of the mirrors.
+
#* Cleaning of the mirrors. (Greg, Keith) <span>&#10003;</span>
#* Remarking the Fiber cable label.
+
#* Remarking and repositioning the Fiber cable label. (Fernando/Chris) <span>&#10003;</span>
#* Installation tray.
+
#* PMT mounting plate spacer (Bobby) <span>&#10003;</span>
#* Installation sheets.
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#* Installation tray. (Mark/Keith) <span>&#10003;</span>
 +
#* Installation spacer. (Bobby) <span>&#10003;</span>
 +
 
 +
==2019==
 +
# Temperature reduction for the DIRC FPGAs.
 +
# Water quality setup, 3D printing the box.
 +
# Darkening. <span>&#10003;</span>
 +
# Uni-strut reinforcement for the distribution boxes. <span>&#10003;</span>
 +
# Airflow sensor <span>&#10003;</span>
 +
# Opening both DIRC boxes in January:
 +
#* Check mirror quality <span>&#10003;</span>
 +
#* Check anodize quality <span>&#10003;</span>
 +
#* Check water tightness of the diffuser assembly. <span>&#10003;</span>
 +
# North Box:
 +
#* Check corner interference. <span>&#10003;</span>
 +
#* Silicone around the wielding spot. <span>&#10003;</span>
 +
# South Box:
 +
#* Check the chipped corner water seal for both spots
 +
 
 +
==2020 Summer DIRC To-do List==
 +
# Hall work:
 +
#* Water level sensor installation
 +
#**Total:  2 days. 1 day testing + 1 day installation
 +
#* Darkening leak check
 +
#** Total: 1 day
 +
#* Modification on vent exit to reduce FPGA temperature
 +
#** Total: 3 days. 1 day diagnose, 1 day test and 1 day installation. Excluding time for designing time.
 +
#* DIRC Diffuser seal issue
 +
#** Total: 2 days. 1 day test and 1 day installation. Excluding time for water seal test
 +
#* Contaminated mirror replacement in north upper OB
 +
#** Total: 1 days. Uninstall + Disassembly: 1 day; mirror removal + setting up clean area, mirror gluing+ curing: 3 days; silicone seal +  cleaning + assembly: 1 days; installation: 1 day. Excluding time for water seal test
 +
#* Inspect the south lower OB
 +
#** 1 day
 +
#** If mirror problem, adding 6 more days for mirror replacement.
 +
# Non Hall Work:
 +
#* Testing spare DIRC modules
 +
#* Control and operation
 +
#** Alarm modification strategy 
 +
#** Resolving (double checking) DIRC hole in occupancy before run starts
 +
#** Dis-entangle DIRC interlock and interlock reset from FCAL and CCOM
 +
#** Individual (stand alone) SiPM TDA offset
 +
#* Tile FPGA voltage regulation issue.
 +
#* Recover loan-out (Duke SOLID group) MOROC chips

Latest revision as of 13:49, 10 April 2020

2018

  1. Priority list:
    • Laser alignment and generating mis-alignment table (Bill, Andrew).
    • Feedthrough opening angle measurement and fish tank (Bill, Fernando).
    • Light monitors testing and mounting (Bill, Keith).
    • DIRC module cabling strategy (Bill/Andrew).
    • Hole opening on the backplate (Keith).
    • Hole opening on the of the PMT mounting plate (Tim, Keith, Bobby).
    • Plastic bolts and screws for the FPGA board. (Chris)
    • Recover PMT #9 and 10 and perform test
    • Spare micro-BNC cable for the big box. (Omen)
    • Cleaning of the mirrors. (Greg, Keith)
    • Remarking and repositioning the Fiber cable label. (Fernando/Chris)
    • PMT mounting plate spacer (Bobby)
    • Installation tray. (Mark/Keith)
    • Installation spacer. (Bobby)

2019

  1. Temperature reduction for the DIRC FPGAs.
  2. Water quality setup, 3D printing the box.
  3. Darkening.
  4. Uni-strut reinforcement for the distribution boxes.
  5. Airflow sensor
  6. Opening both DIRC boxes in January:
    • Check mirror quality
    • Check anodize quality
    • Check water tightness of the diffuser assembly.
  7. North Box:
    • Check corner interference.
    • Silicone around the wielding spot.
  8. South Box:
    • Check the chipped corner water seal for both spots

2020 Summer DIRC To-do List

  1. Hall work:
    • Water level sensor installation
      • Total: 2 days. 1 day testing + 1 day installation
    • Darkening leak check
      • Total: 1 day
    • Modification on vent exit to reduce FPGA temperature
      • Total: 3 days. 1 day diagnose, 1 day test and 1 day installation. Excluding time for designing time.
    • DIRC Diffuser seal issue
      • Total: 2 days. 1 day test and 1 day installation. Excluding time for water seal test
    • Contaminated mirror replacement in north upper OB
      • Total: 1 days. Uninstall + Disassembly: 1 day; mirror removal + setting up clean area, mirror gluing+ curing: 3 days; silicone seal + cleaning + assembly: 1 days; installation: 1 day. Excluding time for water seal test
    • Inspect the south lower OB
      • 1 day
      • If mirror problem, adding 6 more days for mirror replacement.
  2. Non Hall Work:
    • Testing spare DIRC modules
    • Control and operation
      • Alarm modification strategy
      • Resolving (double checking) DIRC hole in occupancy before run starts
      • Dis-entangle DIRC interlock and interlock reset from FCAL and CCOM
      • Individual (stand alone) SiPM TDA offset
    • Tile FPGA voltage regulation issue.
    • Recover loan-out (Duke SOLID group) MOROC chips