CAEN V792N ADC

This short section describes the behavior of the V792N ADC from CAEN. In the current setup a blue LED is coupled to an XP2020 PMT by an optical fiber and the light intensity is adjusted such that the PMT provides a signal between about 10mV and 40mV. The HV of the PMT is set at -1700V. The signal is connected to an amplifier of 10 and then connected to a linear FAN IN/OUT. The DC output of the FAN can be adjusted and is changed between 0 and 15mV in this test. The ADC V792N is a charge integrating ADC with a 12bit digitizer and has a sensitivity of 100fC per channel with a maximum at 400pC. There is a built in threshold for each channel that varies between about 50 and 60 bins. In this test channel 4 of the ADC is used and its threshold is found to be about 55 as shown in the next plot. This corresponds to a threshold of 5.5pC. The gate length is set at 63.6ns.

Not that the red histogram is when a signal from the PMT was present but the total integrated charge is below 55*50fC and hence below the threshold of the ADC channel. The pink curve is a fit to the black histogram that is the pedestal generated by a random trigger not correlated to the LED trigger.
In the following the DC offset is increased in steps to find the level where the total integrated charge from the LED trigger event is above threshold. The following plots show the ADC spectrum of the same channel at DC offsets of -3.5mV, -3.9mV, -4.0mV, -4.2mV, -5.0mV and -9.6mV:


One can see that at a -3.9mV DC offset the signal starts to appear meaning that the integrated value is above the built in threshold. At -4.0mV DC offset the ADC signal is clearly discernible the separated from the pedestal. The smaller peak in red around channel 54 represent those events where the total integrated charge is below the built in threshold. At a DC offset of -4.2mV almost all events are above the threshold. From this point on any additional DC offset will move the whole ADC spectrum to higher values. The width of the pedestal should not change and also the distance between the pedestal and the signal peak should not change due to such a shift. This behavior is clearly seen in the last two plots where the DC offset has been set to -5.0mV and -9.6mV respectively.