Feb 10, 2011 SiPM Electrical and Cooling

Background information

• Files for discussion
• Hall D BCAL Readout Mechanical Concept (Jim Fochtman)

Action Items from previous meetings

1. Run his cooling model simulation for the situation when the electronics was turned off (Jim)
2. Update Npe numbers on dynamic range table to include effect of attenuation length (Elton)

Tentative Agenda

1. Announcements
2. Schedule, reporting, and manpower (Elton)
3. First article testing (Carl and Yi)
4. Mechanical cooling (Jim)
5. Temperature compensation (Jack)
6. Preamp-summing (Fernando)
7. Discussion

Minutes

Attendees: Elton, Fernando, Tim, Chuck, Jim, Carl, Yi

1. Announcements
2. Schedule, reporting, and manpower (Elton)
   • New ETC change request indicates we will need about 2 more people on this project, mostly in electrical sector.
   • Fernando and Jack should check whether additional persons are required. Fernando said that Chris Stanislav will assist with the board design. He is in the process of hiring another tech.
3. First article testing (Carl and Yi)
   • Carl is installing a backup DAQ.
   • Carl will work with Fernando to reduce ringing on signals from the new amplifier board.
   • John McKisson will help with any histograming requirements.
   • Yi has ordered parts and all have been received
   • He has written all the drivers for the devices, and is now working on integration.
   • The test setup should be ready in about a week and shakedown will take another week. It should be ready when the first article pieces arrive first week in March.
4. Mechanical cooling (Jim)
   • Considerable discussion on the present mechanical design. The goal is to have a volume enclosure starting from the end of the Bcal to the preamp/sum board. With this design the heat of the board can be vented to the outside.
   • Connectors are suggested for the end of the preamp/sum board to allow for gas tightness
   • Most of the design up to the electronic boards is fixed and can be ordered.
5. Temperature compensation (Jack) Jack is in Baltimore, but sent the following updates
   1. I have a solution for 3 - 7 C that will keep divider errors within 6% with nominal 1% (EIA-96) resistor values. The error can stay within about 4% if the trim resistors are selected from the 0.5% values (EIA-192).
   2. This solution appears to be also very close for operation at 18 - 22 C but has an offset. This could be compensated for by modifying the Vsupply when operating at the 20 C range.
   3. This approach works for any arbitrary Vbr for a SiPM but imposes a requirement that we group the SiPMs so that the values of the Vbr are within 0.2 V or better. Error drops within 5% if the binning is by 0.1V Vbr steps. I think that may be difficult. Grouping the SiPM devices that share similar Vbr *may* not allow this simpler solution given the number of devices and the number of bias supplies.
   4. I'm now looking more closely at a slightly more complex passive solution that would still require binning the devices by Vbr but could widen the range to perhaps 0.25V or 0.4V. This solution uses a pre-trim divider network to widen the allowable Vsupply. It adds two more resistors to each passive divider (all EIA-96).
   5. The total power consumption would again rise - but only slightly. The trade-off there is power consumption for immunity to count rate gain shifts.
6. Preamp-summing (Fernando)
   • Fernando suggested a mini-PC board that could connect signal lines from the SiPM connector onto a single line for connection to the electronic boards.
   • This suggestion was well-received, as it would greatly reduce the size of cutouts in the boards, as well as additional connectors.
7. Discussion